Reduction of connections for multibus organization

The multibus interconnection network is an attractive solution for connecting processors and memory modules in a multiprocessor with shared memory. It provides a throughput which is intermediate between the single bus and the crossbar, with a corresponding intermediate cost.Postprint (published version

A polymorphic reconfigurable emulator for parallel simulation

Microprocessor and arithmetic support chip technology was applied to the design of a reconfigurable emulator for real time flight simulation. The system developed consists of master control system to perform all man machine interactions and to configure the hardware to emulate a given aircraft, and numerous slave compute modules (SCM) which comprise the parallel computational units. It is shown that all parts of the state equations can be worked on simultaneously but that the algebraic equations cannot (unless they are slowly varying). Attempts to obtain algorithms that will allow parellel updates are reported. The word length and step size to be used in the SCM's is determined and the architecture of the hardware and software is described

Reading list of selected PASM-related publications

Prepared for a chapter to be published in the forthcoming Encyclopedia of Parallel Computing by Springer Publishing Company. The Encyclopedia will contain a broad coverage of the field and will include entries on machine organization, programming, algorithms, and applications. The broad coverage, together with extensive pointers to the literature for in-depth study, is expected to make the Encyclopedia a useful reference tool in parallel computing

Design of a monitor for the debugging and development of multiprocessing process control systems : a thesis presented in partial fulfilment of the requirements for the degree of Master of Technology in Computing Technology at Massey University

This thesis describes the design of a general purpose tool for debugging and developing multimicroprocessor process control systems. With the decreasing pnce of computers, multimicroprocessors are increasingly being used for process control. However, the lack of published information on multiprocessing systems and distributed systems has meant that methodologies and tools for debugging and developing such systems have been slow to develop. The monitor designed here is system independent, a considerable advantage over other such tools that are currently available

Design and evaluation of multimicroprocessor systems

Thesis (M.S.)--Massachusetts Institute of Technology, Alfred P. Sloan School of Management, 1980.MICROFICHE COPY AVAILABLE IN ARCHIVES AND DEWEY.Includes bibliographical references.by Amar Gupta.M.S

Microprocessor- Oriented Algorithms for Data Communications

Data modem design has attracted a lot of scientific and commercial interest for more than three decades now. The field is important from a scientific point of view, since reliable data communications require very sophisticated solutions to many associated problems. From a commercial point of view its importance arises from the ever- rising needs for Computer networking and distributed processing in general. Modem algorithms are real-time in nature, so adequate technological support is important for modem design development. Advances in VLSI are opening new possibilities in this area and current trends toward integration of computing and communications are placing new demands on its further development. One can say that data modem design is entering its renaissance and this fact was our motivation in preparing this text. The objective is to bridge the gap between the increasing number of published papers on modem design and implementation, and the rapidly growing interest in the field. Included in the text are topics to introduce and familiarize the reader with modem design. Topics covered include: microprocessor applications in communications, data modem types, microprocessor and VLSI types, and technological impacts on design. Finally, we address the hardware issues such as the processor elements and interfacing, and software issues like the digital filter implementation. A comprehensive bibliography on modem design and implementation is also provided. With this bibliography one can research VLSI/microprocessor-based data modem design easily and thoroughly

A new taxonomy for distributed computer systems based upon operating system structure

Characteristics of the resource structure found in the operating system are considered as a mechanism for classifying distributed computer systems. Since the operating system resources, themselves, are too diversified to provide a consistent classification, the structure upon which resources are built and shared are examined. The location and control character of this indivisibility provides the taxonomy for separating uniprocessors, computer networks, network computers (fully distributed processing systems or decentralized computers) and algorithm and/or data control multiprocessors. The taxonomy is important because it divides machines into a classification that is relevant or important to the client and not the hardware architect. It also defines the character of the kernel O/S structure needed for future computer systems. What constitutes an operating system for a fully distributed processor is discussed in detail

Robot Control Computation in Microprocessor systems with Multiple Arithmetic Processors

In this paper we address the problem of designing a high performance robot controller with multiple arithmetic processing units (APU’s). One attractive feature about this controller is that a minimum number of special purpose hardware components are needed, and in fact off the shelf components can be used. In the controller described in this paper, one main processor (MPU) schedules a number of APU’s to produce the computational throughput. In this design an efficient scheduling algorithm plays the most important role in the system performance. DF/IHS* algorithm [8] is an efficient algorithm that solves strong NP-hard problems of scheduling a set of particularly ordered computational tasks onto a multiprocessor system. When interprocessor communication overheads are appreciable, it is not very effective in providing a practical near optimum schedule. It fails to consider the problem of contention for shared resources. In this paper we present new multiprocessor scheduling algorithm, which minimizes the effect of overhead and by doing so it reduces the effect of contention. We used this scheduling algorithm to derive the operational instructions of the APU’s and the MPU for our multiple APU-based robot controller. Simulations show six Motorola MC 68881 APU’s can be used to generate the robotic control computations in approximately 2.5 milliseconds. The control computations involve inverse dynamic calculations, forward kinematics, inverse kinematics, and trajectory computations. *DF/IHS = Depth First/Initial Heuristic Search, this is a derivative of CP/MISF (critical path/Most Immediate Successor First) scheduling algorithm, see [8]

Characterization of robotics parallel algorithms and mapping onto a reconfigurable SIMD machine

The kinematics, dynamics, Jacobian, and their corresponding inverse computations are six essential problems in the control of robot manipulators. Efficient parallel algorithms for these computations are discussed and analyzed. Their characteristics are identified and a scheme on the mapping of these algorithms to a reconfigurable parallel architecture is presented. Based on the characteristics including type of parallelism, degree of parallelism, uniformity of the operations, fundamental operations, data dependencies, and communication requirement, it is shown that most of the algorithms for robotic computations possess highly regular properties and some common structures, especially the linear recursive structure. Moreover, they are well-suited to be implemented on a single-instruction-stream multiple-data-stream (SIMD) computer with reconfigurable interconnection network. The model of a reconfigurable dual network SIMD machine with internal direct feedback is introduced. A systematic procedure internal direct feedback is introduced. A systematic procedure to map these computations to the proposed machine is presented. A new scheduling problem for SIMD machines is investigated and a heuristic algorithm, called neighborhood scheduling, that reorders the processing sequence of subtasks to reduce the communication time is described. Mapping results of a benchmark algorithm are illustrated and discussed