An 8-PSK TDMA uplink modulation and coding system

The combination of 8-phase shift keying (8PSK) modulation and greater than 2 bits/sec/Hz drove the design of the Nyquist filter to one specified to have a rolloff factor of 0.2. This filter when built and tested was found to produce too much intersymbol interference and was abandoned for a design with a rolloff factor of 0.4. The preamble is limited to 100 bit periods of the uncoded bit period of 5 ns for a maximum preamble length of 500 ns or 40 8PSK symbol times at 12.5 ns per symbol. For 8PSK modulation, the required maximum degradation of 1 dB in -20 dB cochannel interference (CCI) drove the requirement for forward error correction coding. In this contract, the funding was not sufficient to develop the proposed codec so the codec was limited to a paper design during the preliminary design phase. The mechanization of the demodulator is digital, starting from the output of the analog to digital converters which quantize the outputs of the quadrature phase detectors. This approach is amenable to an application specific integrated circuit (ASIC) replacement in the next phase of development

Log Likelihood Ratio Soft Decision Demapper: An FPGA Implementation for a High Data Rate Modem

This Project is sponsored by The MITRE Corporation to develop an FPGA implementation of a Log Likelihood Ratio (LLR) soft decision demapper for a High Data Rate (HDR) modem. The main goal of this project is to add support for higher order modulation up to 32APSK for HDR and high bandwidth efficiency. Through preliminary research, several DVB-S2 soft decision LLR algorithms are investigated for different modulation schemes in order to decide which algorithm will be implemented in synthesizable Hardware Description Language (HDL). Algorithms are analyzed based on performance simulation in MATLAB and complexity analysis. The goal is to improve the performance of current system and provide recommendations for future designs of the soft decision demapper for DVB-S2

Advanced Modulation and Coding Technology Conference

The objectives, approach, and status of all current LeRC-sponsored industry contracts and university grants are presented. The following topics are covered: (1) the LeRC Space Communications Program, and Advanced Modulation and Coding Projects; (2) the status of four contracts for development of proof-of-concept modems; (3) modulation and coding work done under three university grants, two small business innovation research contracts, and two demonstration model hardware development contracts; and (4) technology needs and opportunities for future missions

Planar Approximation for the Least Reliable Bit Log-Likelihood Ratio of 8-PSK Modulation

The optimum decoding of component codes in block coded modulation (BCM) schemes requires the use of the log-likelihood ratio (LLR) as the signal metric. An approximation to the LLR for the least reliable bit (LRB) in an 8-PSK modulation based on planar equations with fixed-point arithmetic is developed that is both accurate and easily realisable for practical BCM schemes. Through an error power analysis and an example simulation it is shown that the approximation results in less than 0.06 dB in degradation over the exact expression at an Es/N0 of 10 dB. It is also shown that the approximation can be realised in combinatorial logic using roughly 7300 transistors. This compares favourably to a look-up table approach in typical systems

Error control techniques for satellite and space communications

Two aspects of the work for NASA are examined: the construction of multi-dimensional phase modulation trellis codes and a performance analysis of these codes. A complete list is contained of all the best trellis codes for use with phase modulation. LxMPSK signal constellations are included for M = 4, 8, and 16 and L = 1, 2, 3, and 4. Spectral efficiencies range from 1 bit/channel symbol (equivalent to rate 1/2 coded QPSK) to 3.75 bits/channel symbol (equivalent to 15/16 coded 16-PSK). The parity check polynomials, rotational invariance properties, free distance, path multiplicities, and coding gains are given for all codes. These codes are considered to be the best candidates for implementation of a high speed decoder for satellite transmission. The design of a hardware decoder for one of these codes, viz., the 16-state 3x8-PSK code with free distance 4.0 and coding gain 3.75 dB is discussed. An exhaustive simulation study of the multi-dimensional phase modulation trellis codes is contained. This study was motivated by the fact that coding gains quoted for almost all codes found in literature are in fact only asymptotic coding gains, i.e., the coding gain at very high signal to noise ratios (SNRs) or very low BER. These asymptotic coding gains can be obtained directly from a knowledge of the free distance of the code. On the other hand, real coding gains at BERs in the range of 10(exp -2) to 10(exp -6), where these codes are most likely to operate in a concatenated system, must be done by simulation

Error control techniques for satellite and space communications

Shannon's capacity bound shows that coding can achieve large reductions in the required signal to noise ratio per information bit (E sub b/N sub 0 where E sub b is the energy per bit and (N sub 0)/2 is the double sided noise density) in comparison to uncoded schemes. For bandwidth efficiencies of 2 bit/sym or greater, these improvements were obtained through the use of Trellis Coded Modulation and Block Coded Modulation. A method of obtaining these high efficiencies using multidimensional Multiple Phase Shift Keying (MPSK) and Quadrature Amplitude Modulation (QAM) signal sets with trellis coding is described. These schemes have advantages in decoding speed, phase transparency, and coding gain in comparison to other trellis coding schemes. Finally, a general parity check equation for rotationally invariant trellis codes is introduced from which non-linear codes for two dimensional MPSK and QAM signal sets are found. These codes are fully transparent to all rotations of the signal set

Turbo Encoder Design for Symbol Interleaved Parallel Concatenated Trellis Coded Modulation

This paper addresses turbo-encoder design for coding with high spectral efficiency using parallel concatenated trellis-coded modulation and symbol interleaving. The turbo-encoder design involves the constituent encoder design and the interleaver design. The constituent encoders are optimized for symbol-wise effective free distance, and each has an infinite symbol-wise impulse response. We identify the canonical structures for the constituent encoder search space. In many cases of practical interest, the optimal structure for these constituent encoders connects the memory elements in a single row. This single row generally applies to turbo code constituent encoders for parallel concatenation and is not restricted to symbol interleaving. To lower the error floor, a new semi-random interleaver design criteria and a construction method extends the spread-interleaver concept introduced by Divsalar and Pollara (1995). Simulation results show that the proposed system employing symbol interleaving can converge at a lower signal-to-noise ratio than previously reported systems. We report simulation results between 0.5 and 0.6 db from constrained capacity for rates of 2 and 4 bits/s/Hz

Satellite Data Transmission (SDT) requirement

An 85 Mb/s modem/codec to operate in a 34 MHz C-band domestic satellite transponder at a system carrier to noise power ratio of 19.5 dB is discussed. Characteristics of a satellite channel and the approach adopted for the satellite data transmission modem/codec selection are discussed. Measured data and simulation results of the existing 50 Mbps link are compared and used to verify the simulation techniques. Various modulation schemes that were screened for the SDT are discussed and the simulated performance of two prime candidates, the 8 PSK and the SMSK/2 are given. The selection process that leads to the candidate codec techniques are documented and the technology of the modem/codec candidates is assessed. Costs of the modems and codecs are estimated