Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication

Digitally-Assisted RF-Analog Self Interference Cancellation for Wideband Full-Duplex Radios

The ever-increasing demand for more data from users is pushing the development of alternative wireless technologies to improve upon network capacity. Full-Duplex radios provide an exciting opportunity to theoretically double the available spectral efficiency of wireless networks by simultaneously transmitting and receiving signals in the same frequency band. The main challenge that is presented in the implementation of a full-duplex radio is the high power transmitter leaking to the sensitive receiver chain and masking the desired receive signal to be decoded. This transmitter leakage is referred to as self interference and it is required that this self interference signal be cancelled below the receiver noise floor to achieve the full benefits of a full-duplex radio. Cancellation of the self interference signal is realized through several techniques, categorized as passive suppression, digital cancellation, and analog cancellation. These methods all have their challenges in achieving the full amount of cancellation necessary and therefore all three techniques are typically employed in the system. In this thesis, a novel digitally assisted radio frequency (RF) analog self interference canceller is proposed to suppress the self interference signal before the receiver chain for wide modulation bandwidth signals. This canceller augments minimum complexity RF-analog interference cancellation hardware that uses an RF vector multiplier in combination with a flexible digital rational function finite impulse response filter. The simple topology reduces the number of impairments added to the system through the analog components and identifies the parameters of the proposed filter in a deterministic and single iteration algorithm. The hardware proof-of-concept prototype is built using off-the-shelf RF-analog components and demonstrates excellent cancellation performance. Using four TX test signals with modulation bandwidths of 20~MHz, 40~MHz, 80~MHz, and 120~MHz, the self interference canceller achieves a minimum of 50~dB, 47~dB, 42~dB, and 40~dB of cancellation respectively. This thesis reviews the previously proposed self interference cancellation topologies, system non-idealities that provide challenges for full-duplex implementation, and the realization of the proposed RF-analog self interference canceller

Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios

Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

The Experimental Design of Radio-over-Fibre System for 4G Long Term Evolution

The 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) is the potential key to meet the exponentially increasing demand of the mobile end users. The entire LTE network architecture and signal processing is carried out at the enhanced NodeB (eNB) level, hence the increased complexity and cost. Therefore, it is not efficient to deploy eNB for the purpose of extending the network coverage. As a solution, deployment of relay node (RN), with radio-over-fibre (RoF) acting as the interface between eNB and RN is proposed. Due to the high path loss and multipath fading, wireless interface would not be the ideal channel between eNB and RN. A detailed investigation is carried out by comparing the Rayleigh multipath fading channel with the optical fibre channel, where the latter achieved a ~31 dB of signal-to-noise ratio (SNR) gain. The distributed feedback laser (DFB) is selected as the direct modulated laser (DML) source, where the modulation method introduces a positive frequency chirp (PFC). The existing mathematical expression does not precisely explain on how the rate equations contribute to PFC. Therefore, an expression for PFC is proposed and derived from the carrier and photon densities of the rate equations. Focusing on theoretical development of DML based RoF system, a varying fast Fourier transform (FFT) scheme is introduced into LTE-Advanced (LTE-A) technology as an alternative design to the carrier aggregation. A range of FFT sizes are investigated with different levels of optical launch power (OLP), the optimum OLP has been defined to be within the range of ~-6 to 0 dBm, which is known as the intermixing region. It is found that FFT size-128 provides improved average system efficiency of ~54% and ~65% in comparison to FFT size-64 and FFT size-128, respectively, within the intermixing region. While fixing FFT size to 128, the investigation is diverted to the optimisation of optical modulators. The author revealed that the performance of dual electrode-Mach Zehnder modulator (DE-MZM) is superior to both DML scheme and single electrode (SE)-MZM, where DE-MZM achieved a transmission span of 88 km and 71 km for 16-quadrature amplitude modulation (QAM) and 64-QAM, respectively. At the initial experimental link design and optimisation stage, an optimum modulation region (OMR) is proposed at the optical modulation index (OMI) of 0.38, which resulted in an average error vector magnitude (EVM) of ~1.01% for a 10 km span. The EVM of ~1.01% is further improved by introducing the optimum OLP region at –2 dBm, where the observed average EVM trimmed to ~0.96%. There is no deviation found in the intermixing region by transmitting the LTE signal through a varying transmission span of 10 to 60 km, additionally, it was also revealed that the LTE RoF nonlinear threshold falls above the OLP of 6 dBm. The proposed system was further developed to accommodate 2×2 multiple-input and multiple-output (MIMO) transmission by utilising analogue frequency division multiplexing (FDM) technique. The studies procured that the resulting output quality of signal at 2 GHz and 2.6 GHz is almost identical with a twofold gain in the peak data rate and no occurrence of intermodulation (IMD). In order to emulate the complete LTE RoF solution, an experimental design of full duplex frequency division duplex (FDD) system with dense wavelength division multiplexing (DWDM) architecture is proposed. It is found that channel spacing of 50 MHz between the downlink (DL) and uplink (UL) introduces severe IMD distortion, where an adjacent channel leakage ratio (ACLR) penalty of 14.10 dB is observed. Finally, a novel nonlinear compensation technique utilising a direct modulation based frequency dithering (DMFD) scheme is proposed. The LTE RoF system average SNR gain observed at OLP of 10 dBm for the 50 km transmission span is ~5.97 dB. External modulation based frequency dithering (EMFD) exhibits ~3 dB of average SNR gain over DMFD method

Semiconductor Optical Amplifiers and mm-Wave Wireless Links for Converged Access Networks

Future access networks are converged optical-wireless networks, where fixed-line and wireless services share the same infrastructure. In this book, semiconductor optical amplifiers (SOA) and mm-wave wireless links are investigated, and their use in converged access networks is explored: SOAs compensate losses in the network, and thereby extend the network reach. Millimeter-wave wireless links substitute fiber links when cabling is not economical