LMS-Based RF BIST Architecture for Multistandard Transmitters

Article accepté pour publicationInternational audienceSoftware defined radios (SDR) platforms are increasingly complex systems which combine great flexibility and high performance. These two characteristics, together with highly integrated architectures make production test a challenging task. In this paper, we introduce an Radio Frequency (RF) Built-in Self-Test (BIST) strategy based on Periodically Nonuniform Sampling of the signal at the output stages of multistandard radios. We leverage the I/Q ADC channels and the DSP resources to extract the bandpass waveform at the output of the power amplifier (PA). Analytic expressions and simulations show that our time-interleaved conversion scheme is sensitive to time-skew. We propose a time-skew estimation technique based on a Least Mean Squares (LMS) algorithm to solve this problem. Simulation results show that we can effectively reconstruct the bandpass signal of the output stage using this architecture, opening the way for a complete RF BIST strategy for multistandard radios

A flexible BIST strategy for SDR transmitters

International audienceSoftware-defined radio (SDR) development aims for increased speed and flexibility. The advent of these system level requirements on the physical layer (PHY) access hardware is leading to more complex architectures, which together with higher levels of integration pose a challenging problem for product testing. For radio units that must be field-upgradeable without specialized equipment, Built-in Self-Test (BIST) schemes are arguably the only way to ensure continued compliance to specifications. In this paper we introduce a loopback RF BIST technique that uses Periodically Nonuniform Sampling (PNS2) of the transmitter (TX) output to evaluate compliance to spectral mask specifications. No significant hardware costs are incurred due to the re-use of available RX resources (I/Q ADCs, DSP, GPP, etc.). Simulation results of an homodyne TX demonstrate that Adjacent Channel Power Ratio (ACPR) can be accurately estimated. Future work will consist in validating our loopback RF BIST architecture on an in-house SDR testbed

Adaptive Estimation and Compensation of the Time Delay in a Periodic Non-uniform Sampling Scheme

High sampling rate Analog-to-Digital Converters (ADCs) can be obtained by time-interleaving low rate (and thus low cost) ADCs into so-called Time-Interleaved ADCs (TI-ADCs). Nevertheless increasing the sampling frequency involves an increasing sensibility of the system to desynchronization between the different ADCs that leads to time-skew errors, impacting the system with non linear distortions. The estimation and compensation of these errors are considered as one of the main challenge to deal with in TI-ADCs. Some methods have been previously proposed, mainly in the field of circuits and systems, to estimate the time-skew error but they mainly involve hardware correction and they lack of flexibility, using an inflexible uniform sampling reference. In this paper, we propose to model the output of L interleaved and desynchronized ADCs with a sampling scheme called Periodic Non-uniform Sampling of order L (PNSL). This scheme has been initially proposed as an alternative to uniform sampling for aliasing cancellation, particularly in the case of bandpass signals. We use its properties here to develop a flexible on-line digital estimation and compensation method of the time delays between the desynchronized channels. The estimated delay is exploited in the PNSL reconstruction formula leading to an accurate reconstruction without hardware correction and without any need to adapt the sampling operation. Our method can be used in a simple Built-In Self-Test (BIST) strategy with the use of learning sequences and our model appears more flexible and less electronically expensive, following the principles of “Dirty Radio Frequency” paradigm: designing imperfect analog circuits with subsequently digital corrections of these imperfections

Adaptive Estimation and Compensation of the Time Delay in a Periodic Non-uniform Sampling Scheme

High sampling rate Analog-to-Digital Converters (ADCs) can be obtained by time-interleaving low rate (and thus low cost) ADCs into so-called Time-Interleaved ADCs (TI-ADCs). Nevertheless increasing the sampling frequency involves an increasing sensibility of the system to desynchronization between the different ADCs that leads to time-skew errors, impacting the system with non linear distortions. The estimation and compensation of these errors are considered as one of the main challenge to deal with in TI-ADCs. Some methods have been previously proposed, mainly in the field of circuits and systems, to estimate the time-skew error but they mainly involve hardware correction and they lack of flexibility, using an inflexible uniform sampling reference. In this paper, we propose to model the output of L interleaved and desynchronized ADCs with a sampling scheme called Periodic Non-uniform Sampling of order L (PNSL). This scheme has been initially proposed as an alternative to uniform sampling for aliasing cancellation, particularly in the case of bandpass signals. We use its properties here to develop a flexible on-line digital estimation and compensation method of the time delays between the desynchronized channels. The estimated delay is exploited in the PNSL reconstruction formula leading to an accurate reconstruction without hardware correction and without any need to adapt the sampling operation. Our method can be used in a simple Built-In Self-Test (BIST) strategy with the use of learning sequences and our model appears more flexible and less electronically expensive, following the principles of “Dirty Radio Frequency” paradigm: designing imperfect analog circuits with subsequently digital corrections of these imperfections

Nonlinear Equalization and Digital Pre-Distortion Techniques for Future Radar and Communications Digital Array Systems

Modern radar (military, automotive, weather, etc.) and communication systems seek to leverage the spatio-spectral efficiency of phased arrays. Specifically, there is an increasingly large demand for fully-digital arrays, with each antenna element having its own transmitter and receiver. Further, in order to makes these systems realizable, low-cost, low-complexity solutions are required, often sacrificing the system's linearity. Lower linearity paired with the inherent lack of RF spacial filtering can make these highly digital systems vulnerable to high-power interferering signals-- potentially introducing spectral regrowth and/or gain compression, distorting the signal-of-interest. Digital linearization solutions such as Digital Pre-Distiortion (DPD) and Nonlinear Equalization (NLEQ) have been shown to effectively mitigate nonlinearities for transmitters and receivers, respectively. Further, DPD and NLEQ seek to extend the effective dynamic range of digital arrays, helping the systems reach their designed dynamic range improvement of $10\log_{10}(N)$~dB, where $N$ is the number of transmitters/receivers. However, the performance of these solutions is ultimately determined by training model and waveform. Further, the nonlinear characteristics of a system can change with temperature, frequency, power, time, etc., requiring a robust calibration technique to maintain a high-level of nonlinear mitigation. This dissertation reviews the different types of nonlinear models and the current NLEQ and DPD algorithms for digital array systems. Further, a generalized calibration waveform for both NLEQ and DPD is proposed, allowing a system to maximize its dynamic range over power and frequency. Additionally, an \textit{in-situ} calibration method, leveraging the inherent mutual coupling in an array, is proposed as a solution to maintaining a high level of performance in a fielded digital array system over the system's lifetime. The combination of the proposed training waveform and \textit{in-situ} calibration technique prove to be very effective at adaptively creating a generalized solution to extending the dynamic range of future low-cost digital array systems

Post Conversion Correction of Non-Linear Mismatches for Time Interleaved Analog-to-Digital Converters

Time Interleaved Analog-to-Digital Converters (TI-ADCs) utilize an architecture which enables conversion rates well beyond the capabilities of a single converter while preserving most or all of the other performance characteristics of the converters on which said architecture is based. Most of the approaches discussed here are independent of architecture; some solutions take advantage of specific architectures. Chapter 1 provides the problem formulation and reviews the errors found in ADCs as well as a brief literature review of available TI-ADC error correction solutions. Chapter 2 presents the methods and materials used in implementation as well as extend the state of the art for post conversion correction. Chapter 3 presents the simulation results of this work and Chapter 4 concludes the work. The contribution of this research is three fold: A new behavioral model was developed in SimulinkTM and MATLABTM to model and test linear and nonlinear mismatch errors emulating the performance data of actual converters. The details of this model are presented as well as the results of cumulant statistical calculations of the mismatch errors which is followed by the detailed explanation and performance evaluation of the extension developed in this research effort. Leading post conversion correction methods are presented and an extension with derivations is presented. It is shown that the data converter subsystem architecture developed is capable of realizing better performance of those currently reported in the literature while having a more efficient implementation

Design Techniques for High Performance Wireline Communication and Security Systems

As the amount of data traffic grows exponentially on the internet, towards thousands of exabytes by 2020, high performance and high efficiency communication and security solutions are constantly in high demand, calling for innovative solutions. Within server communication dominates todays network data transfer, outweighing between-server and server-to-user data transfer by an order of magnitude. Solutions for within-server communication tend to be very wideband, i.e. on the order of tens of gigahertz, equalizers are widely deployed to provide extended bandwidth at reasonable cost. However, using equalizers typically costs the available signal-to-noise ratio (SNR) at the receiver side. What is worse is that the SNR available at the channel becomes worse as data rate increases, making it harder to meet the tight constraint on error rate, delay, and power consumption. In this thesis, two equalization solutions that address optimal equalizer implementations are discussed. One is a low-power high-speed maximum likelihood sequence detection (MLSD) that achieves record energy efficiency, below 10 pico-Joule per bit. The other one is a phase-shaping equalizer design that suppresses inter-symbol interference at almost zero cost of SNR. The growing amount of communication use also challenges the design of security subsystems, and the emerging need for post-quantum security adds to the difficulties. Most of currently deployed cryptographic primitives rely on the hardness of discrete logarithms that could potentially be solved efficiently with a powerful enough quantum computer. Efficient post-quantum encryption solutions have become of substantial value. In this thesis a fast and efficient lattice encryption application-specific integrated circuit is presented that surpasses the energy efficiency of embedded processors by 4 orders of magnitude.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/146092/1/shisong_1.pd

Échantillonnage Non Uniforme : Application aux filtrages et aux conversions CAN/CNA (Convertisseurs Analogique-Numérique et Numérique/Analogique) dans les télécommunications par satellite

La théorie de l'échantillonnage uniforme des signaux, développée en particulier par C. Shannon, est à l'origine du traitement numérique du signal. Depuis, de nombreux travaux ont été consacrés à l'échantillonnage non uniforme. Celui-ci permet, d'une part, de modéliser les imperfections des dispositifs d'échantillonnage uniforme. D'autre part, l'échantillonnage peut être effectué de manière délibérément non uniforme afin de bénéficier de propriétés particulières, notamment un assouplissement des conditions portant sur le choix de la fréquence moyenne d'échantillonnage. La plupart de ces travaux reste dans un cadre théorique en adoptant des schémas d'échantillonnage et des modèles de signaux simplifiés. Or, actuellement, dans de nombreux domaines d'application, tels que les communications par satellites, la conversion analogique-numérique s'effectue sous des contraintes fortes pour les largeurs de bande mises en jeu, en raison notamment des fréquences très élevées utilisées. Ces conditions opérationnelles accentuent les imperfections des dispositifs électroniques réalisant l'échantillonnage et induisent le choix de modèles de signaux et de schémas d'échantillonnage spécifiques. Cette thèse a pour objectif général d'identifier des modèles d'échantillonnage adaptés à ce cadre applicatif. Ceux-ci s'appliquent à des signaux aléatoires passe-bande, qui constituent un modèle classique en télécommunications. Ils doivent prendre en compte des facteurs technologiques, économiques ainsi que des contraintes bord de complexité et éventuellement intégrer des fonctionnalités propres aux télécommunications. La première contribution de cette thèse est de développer des formules d'échantillonnage non uniforme qui intègrent dans le domaine numérique des fonctionnalités délicates à implémenter dans le domaine analogique aux fréquences considérées. La deuxième contribution consiste à caractériser et à compenser les erreurs de synchronisation de dispositifs d'échantillonnage non uniforme particuliers, à savoir les convertisseurs analogique-numérique entrelacés temporellement, via des méthodes supervisées ou aveugles

ATHENA Research Book, Volume 2

ATHENA European University is an association of nine higher education institutions with the mission of promoting excellence in research and innovation by enabling international cooperation. The acronym ATHENA stands for Association of Advanced Technologies in Higher Education. Partner institutions are from France, Germany, Greece, Italy, Lithuania, Portugal and Slovenia: University of Orléans, University of Siegen, Hellenic Mediterranean University, Niccolò Cusano University, Vilnius Gediminas Technical University, Polytechnic Institute of Porto and University of Maribor. In 2022, two institutions joined the alliance: the Maria Curie-Skłodowska University from Poland and the University of Vigo from Spain. Also in 2022, an institution from Austria joined the alliance as an associate member: Carinthia University of Applied Sciences. This research book presents a selection of the research activities of ATHENA University's partners. It contains an overview of the research activities of individual members, a selection of the most important bibliographic works of members, peer-reviewed student theses, a descriptive list of ATHENA lectures and reports from individual working sections of the ATHENA project. The ATHENA Research Book provides a platform that encourages collaborative and interdisciplinary research projects by advanced and early career researchers