Memristor-Based Digital Systems Design and Architectures

Memristor is considered as a suitable alternative solution to resolve the scaling limitation of CMOS technology. In recent years, the use of memristors in circuits design has rapidly increased and attracted researcher’s interest. Advances have been made to both size and complexity of memristor designs. The development of CMOS transistors shows major concerns, such as, increased leakage power, reduced reliability, and high fabrication cost. These factors have affected chip manufacturing process and functionality severely. Therefore, the demand for new devices is increasing. Memristor, is considered as one of the key element in memory and information processing design due to its small size, long-term data storage, low power, and CMOS compatibility. The main objective in this research is to design memristor-based arithmetic circuits and to overcome some of the Memristor based logic design issues. In this thesis, a fast, low area and low power hybrid CMOS memristor based digital circuit design were implemented. Small and large-scale memristor based digital circuits are implemented and provided a solutions for overcoming the memristor degradation and fan-out challenges. As an example, a 4- bit LFSR has been implemented by using MRL scheme with 64 CMOS devices and 64 memristors. The proposed design is more efficient in terms of the area when compared with CMOS- based LFSR circuits. The simulation results proves the functionality of the design. This approach presents acceptable speed in comparison with CMOS-based design and it is faster than IMPLY-based memrisitive LFSR. The propped LFSR has 841 ps de-lay. Furthermore, the proposed design has a significant power reduction of over 66% less than CMOS-based approach. This thesis proposes implementation of memristive 2-D median filter and extends previously published works on memristive Filter design to include this emerging technology characteristics in image processing. The proposed circuit was designed based on Pt/TaOx/Ta redox-based device and Memristor Ratioed Logic (MRL). The proposed filter is designed in Cadence and the memristive median approved tested circuit is translated to Verilog-XL as a behavioral model. Different 512 _ 512 pixels input images contain salt and pepper noise with various noise density ratios are applied to the proposed median filter and the design successfully has substantially removed the noise. The implementation results in comparison with the conventional filters, it gives better Peak Signal to Noise Ratio (PSNR) and Mean Absolute Error (MAE) for different images with different noise density ratios while it saves more area as compared to CMOS-based design. This dissertation proposes a comprehensive framework for design, mapping and synthesis of large-scale memristor-CMOS circuits. This framework provides a synthesis approach that can be applied to all memristor-based digital logic designs. In particular, it is a proposal for a characterization methodology of memristor-based logic cells to generate a standard cell library for large scale simulation. The proposed framework is implemented in the Cadence Virtuoso schematic-level environment and was veri_ed with Verilog-XL, MATLAB, and the Electronic Design Automation (EDA) Synopses compiler after being translated to the behavioral level. The proposed method can be applied to implement any digital logic design. The frame work is deployed for design of the memristor-based parallel 8-bit adder/subtractor and a 2-D memristive-based median filter

Wave computing with passive memristive networks

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Since CMOS technology approaches its physical limits, the spotlight of computing technologies and architectures shifts to unconventional computing approaches. In this area, novel computing systems, inspired by natural and mostly nonelectronic approaches, provide also new ways of performing a wide range of computations, from simple logic gates to solving computationally hard problems. Reaction-diffusion processes constitute an information processing method, occurs in nature and are capable of massive parallel and low-power computing, such as chemical computing through Belousov-Zhabotinsky reaction. In this paper, inspired by these chemical processes and based on the wave-propagation information processing taking place in the reaction-diffusion media, the novel characteristics of the nanoelectronic element memristor are utilized to design innovative circuits of electronic excitable medium to perform both classical (Boolean) calculations and to model neuromorphic computations in the same Memristor-RLC (M-RLC) reconfigurable network.Peer ReviewedPostprint (author's final draft

Exploring the “resistance change per energy unit” as universal performance parameter for resistive switching devices

© Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/Resistive switching (RS) device (memristor) technology is continuously maturing towards industrial establishment. There are RS devices that demonstrate an “incremental” (analog) switching behavior, whereas others change their state in a binary form. The final achieved resistance is generally a function of the applied pulse characteristics, i.e. amplitude and duration. However, variability —both from device to device but also from cycle to cycle— and the stochastic nature of internal RS phenomena, still hold back any universal tuning approach based solely on these two magnitudes, making also difficult the qualitative comparison between devices with different material compounds owing to the required SET/RESET voltages being dependent on the biasing conditions. In this work we demonstrate experimentally using commercial RS devices from Knowm Inc. that the switching energy is very insensitive to the biasing conditions. We explored experimentally the SET-RESET behavior of bipolar RS devices from the energy point of view. We figured out the quantitative effect of the injected energy to the resistive state of the devices, and proposed an analytical model to explain our observations in the energy consumed by the device during the switching process. Our results lay the foundations for the definition of “resistance change per energy unit” as a performance parameter for this emerging device technology.Peer ReviewedPostprint (author's final draft

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Towards Oxide Electronics:a Roadmap

At the end of a rush lasting over half a century, in which CMOS technology has been experiencing a constant and breathtaking increase of device speed and density, Moore's law is approaching the insurmountable barrier given by the ultimate atomic nature of matter. A major challenge for 21st century scientists is finding novel strategies, concepts and materials for replacing silicon-based CMOS semiconductor technologies and guaranteeing a continued and steady technological progress in next decades. Among the materials classes candidate to contribute to this momentous challenge, oxide films and heterostructures are a particularly appealing hunting ground. The vastity, intended in pure chemical terms, of this class of compounds, the complexity of their correlated behaviour, and the wealth of functional properties they display, has already made these systems the subject of choice, worldwide, of a strongly networked, dynamic and interdisciplinary research community. Oxide science and technology has been the target of a wide four-year project, named Towards Oxide-Based Electronics (TO-BE), that has been recently running in Europe and has involved as participants several hundred scientists from 29 EU countries. In this review and perspective paper, published as a final deliverable of the TO-BE Action, the opportunities of oxides as future electronic materials for Information and Communication Technologies ICT and Energy are discussed. The paper is organized as a set of contributions, all selected and ordered as individual building blocks of a wider general scheme. After a brief preface by the editors and an introductory contribution, two sections follow. The first is mainly devoted to providing a perspective on the latest theoretical and experimental methods that are employed to investigate oxides and to produce oxide-based films, heterostructures and devices. In the second, all contributions are dedicated to different specific fields of applications of oxide thin films and heterostructures, in sectors as data storage and computing, optics and plasmonics, magnonics, energy conversion and harvesting, and power electronics

Continuous-time Algorithms and Analog Integrated Circuits for Solving Partial Differential Equations

Analog computing (AC) was the predominant form of computing up to the end of World War II. The invention of digital computers (DCs) followed by developments in transistors and thereafter integrated circuits (IC), has led to exponential growth in DCs over the last few decades, making ACs a largely forgotten concept. However, as described by the impending slow-down of Moore’s law, the performance of DCs is no longer improving exponentially, as DCs are approaching clock speed, power dissipation, and transistor density limits. This research explores the possibility of employing AC concepts, albeit using modern IC technologies at radio frequency (RF) bandwidths, to obtain additional performance from existing IC platforms. Combining analog circuits with modern digital processors to perform arithmetic operations would make the computation potentially faster and more energy-efficient. Two AC techniques are explored for computing the approximate solutions of linear and nonlinear partial differential equations (PDEs), and they were verified by designing ACs for solving Maxwell\u27s and wave equations. The designs were simulated in Cadence Spectre for different boundary conditions. The accuracies of the ACs were compared with finite-deference time-domain (FDTD) reference techniques. The objective of this dissertation is to design software-defined ACs with complementary digital logic to perform approximate computations at speeds that are several orders of magnitude greater than competing methods. ACs trade accuracy of the computation for reduced power and increased throughput. Recent examples of ACs are accurate but have less than 25 kHz of analog bandwidth (Fcompute) for continuous-time (CT) operations. In this dissertation, a special-purpose AC, which has Fcompute = 30 MHz (an equivalent update rate of 625 MHz) at a power consumption of 200 mW, is presented. The proposed AC employes 180 nm CMOS technology and evaluates the approximate CT solution of the 1-D wave equation in space and time. The AC is 100x, 26x, 2.8x faster when compared to the MATLAB- and C-based FDTD solvers running on a computer, and systolic digital implementation of FDTD on a Xilinx RF-SoC ZCU1275 at 900 mW (x15 improvement in power-normalized performance compared to RF-SoC), respectively

Energy-Efficiency of Conveyor Belts in Raw Materials Industry

This book focuses on research related to the energy efficiency of conveyor transportation. The solutions presented in the Special Issue have an impact on optimizing, and thus reducing, the costs of energy consumption by belt conveyors. This is due, inter alia, to the use of better materials for conveyor belts, which reduce its rolling resistance and noise, and improve its ability to adsorb the impact energy from the material falling on the belt. The use of mobile robots designed to detect defects in the conveyor's components makes the conveyor operation safer, and means that the conveyor works for longer and there are no unplanned stops due to damage

Charged Domain Walls in Ferroelectric Single Crystals

Charged domain walls (CDWs) in proper ferroelectrics are a novel route towards the creation of advancing functional electronics. At CDWs the spontaneous polarization obeying the ferroelectric order alters abruptly within inter-atomic distances. Upon screening, the resulting charge accumulation may result in the manifestation of novel fascinating electrical properties. Here, we will focus on electrical conduction. A major advantage of these ferroelectric DWs is the ability to control its motion upon electrical fields. Hence, electrical conduction can be manipulated, which can enrich the possibilities of current electronic devices e.g. in the field of reconfigurability, fast random access memories or any kind of adaptive electronic circuitry. In this dissertation thesis, I want to shed more light onto this new type of interfacial electronic conduction on inclined DWs mainly in lithium niobate/LiNbO3 (LNO). The expectation was: the stronger the DW inclination towards the polar axis of the ferroelectric order and, hence, the larger the bound polarization charge, the larger the conductivity to be displayed. The DW conductance and the correlation with polarization charge was investigated with a multitude of experimental methods as scanning probe microscopy, linear and nonlinear optical microscopy as well as electron microscopy. We were able to observe a clear correlation of the local DW inclination angle with the DW conductivity by comparing the three-dimensional DW data and the local DW conductance. We investigated the conduction mechanisms on CDWs by temperature-dependent two-terminal current-voltage sweeps and were able to deduce the transport to be given by small electron polaron hopping, which are formed after injection into the CDWs. The thermal activated transport is in very good agreement with time-resolved polaron luminescence spectroscopy. The applicability of this effect for non-volatile memories was investigated in metal-ferroelectric-metal stacks with CMOS compatible single-crystalline films. These films showed unprecedented endurance, retention, precise set voltage, and small leakage currents as expected for single crystalline material. The conductance was tuned and switched according to DW switching time and voltage. The formation of CDWs has proven to be extremely stable over at least two months. The conductivity was further investigated via microwave impedance microscopy, which revealed a DW conductivity of about 100 to 1000 S/m at microwave frequencies of about 1 GHz.:1 INTRODUCTION 1 I THEORETICAL BASICS 5 2 FUNDAMENTALS 7 2.1 Ferroelectricity 7 2.1.1 Spontaneous polarization 8 2.1.2 Domains and domain walls 9 2.1.3 Charged domain walls 13 2.1.4 Conductive domain walls 16 2.2 Visualization of ferroelectric domains and domain walls 21 2.2.1 Light microscopy 22 2.2.2 Second-harmonic generation microscopy 22 2.2.3 Cherenkov second-harmonic generation microscopy 25 2.2.4 Optical coherence tomography 28 2.2.5 Piezo-response force microscopy 30 2.2.6 Ferroelectric lithography 31 2.2.7 Further methods 34 2.3 Lithium niobate and tantalate 37 2.3.1 General Properties 37 2.3.2 Stoichiometry 38 2.3.3 Optical properties 40 2.3.4 Intrinsic and extrinsic defects 43 2.3.5 Polarons 47 2.3.6 Ionic conductivity 51 3 METHODS 53 3.1 Sample Preparation 53 3.1.1 Poling stage 53 3.1.2 Thermal treatment 56 3.1.3 Ion slicing of LNO crystals 57 3.2 Atomic force microscopy 59 3.2.1 Non-contact and contact mode AFM microscopy 59 3.2.2 Piezo-response force microscopy (PFM) 60 3.2.3 Conductive atomic force microscopy (cAFM) 62 3.2.4 Scanning microwave impedance microscopy (sMIM) 63 3.2.5 AFM probes 66 3.3 Laser scanning microscope 67 3.4 Time-resolved luminescence spectroscopy 71 3.5 Energy-resolved photoelectron emission spectromicroscopy 72 II EXPERIMENTS 75 4 RESULTS 77 4.1 Three-dimensional profiling of domain walls 78 4.1.1 Randomly poled LNO and LTO domains 78 4.1.2 Periodically Poled Lithium Niobate 81 4.1.3 AFM-written Domains 83 4.1.4 Thermally treated LNO 84 4.1.5 Laser-written domains 86 4.2 Polarization charge textures 90 4.2.1 Random domains in Mg:LNO and Mg:LTO 90 4.2.2 Thermally-treated LNO 92 4.3 Quasi-phase matching SHG 92 4.4 Photoelectron microspectroscopy 97 4.5 Activated polaron transport 101 4.6 High voltage treated LNO 113 4.7 Conductive domain walls in exfoliated thin-film LNO 115 4.7.1 Conductance maps 116 4.7.2 Resistive switching by conductive domain walls 120 4.8 Microwave impedance microscopy 134 4.8.1 Finite-element method simulation 134 4.8.2 Scanning microwave impedance microscopy 136 5 conclusion & outlook 143 III EPILOGUE 147 a APPENDIX 149 a.1 Laser ablation dynamics on LNO surfaces 149 a.2 XPS across a conductive DW in LNO 150 a.3 XRD of thin-film exfoliated LNO 151 a.4 Domain writing in exfoliated thin-film LNO 152 a.5 Retention in conductance at DWs in thin-film exfoliated LNO 155 a.6 sMIM on DWs in thin-film exfoliated LNO 157 a.7 Domain inversion evolution under a tip by phase-field modeling 159 a.8 Current transients in exfoliated LNO 161 a.9 Surface acoustic wave excitation damping at DWs 162 a.10 Influence of UV illumination on domains in Mg:LNO 162 Acronyms 165 Symbols 169 List of figures 172 List of tables 176 Bibliography 177 Publications 225 Erklärung 233Geladene Domänenwände (DW) in reinen Ferroelektrika stellen eine neue Möglichkeit zur Erzeugung zukünftiger, funktionalisierter Elektroniken dar. An geladenen DW ändert sich die Polarisation sehr abrupt - innerhalb nur weniger Atomabstände. Sofern die dadurch hervorgerufene Ladungsträgeranreicherung elektrisch abgeschirmt werden kann, könnte dies zu faszinierenden elektrischen Eigenschaften führen. Wir möchten uns hierbei jedoch auf die elektrische Leitfähigkeit beschränken. Ein großer Vorteil für die Anwendung leitfähiger DW ist deren kontrollierte Bewegung unter Einwirkung elektrischer Felder. Dies ermöglicht die Manipulation das Ladungstransports, welches zum Beispiel im Bereich der Rekonfigurierbarkeit, schneller Speicherbauelemente und jeder Art von adaptiven elektronischen Schaltungen Anwendung finden kann. In dieser Dissertationsschrift möchte ich diesen neuen Typus grenzflächiger elektronischen Ladungstransports an geladenen DW hauptsächlich am Beispiel von Lithiumniobat/-LiNbO3 (LNO) untersuchen. Die Annahme lautete hierbei: umso stärker die DW zur ferroelektrischen Achse geneigt ist, also desto stärker die gebundene Polarisationsladung und folglich die elektrische DW-Leitfähigkeit. Die elektrische DW-Leitfähigkeit und die Korrelation mit der Polarisationsladung wurde mit verschiedenen experimentellen Methoden wie Rasterkraftmikroskopie, linearer und nichtlinearer optischer Mikroskopie als auch Elektronenmikroskopie untersucht. Es konnte eine klare Korrelation durch Vergleich der dreidimensionalen DW-Aufzeichnungsdaten mit der lokalen Leitfähigkeit gezeigt werden. Wir haben weiterhin den Leitfähigkeitsmechanismus an geladenen DW mittels temperaturabhängiger Strom-Spannungskennlinien untersucht und konnten hierbei einen Hopping-Transport kleiner Elektronenpolaronen nachweisen, welche nach Elektroneninjektion in die geladene DW generiert werden. Der thermisch aktivierte Ladungsträgertransport ist in guter Übereinstimmung mit zeitaufgelöster Polaron-Lumineszenzspektroskopie. Die Anwendbarkeit dieses Effektes für nicht-volatile Speicherbauelemente wurde an Metall-Ferroelektrika-Metall Schichtstrukturen mit CMOS-kompatiblen einkristalliner Filmen untersucht. Die Filme zeigen bisher nichtgesehene Durchhalte- und Speichervermögen, genau definierte Schaltspannung sowie sehr geringe Leckageströme wie dies für einkristalline Materialsysteme erwartet wird. Die Leitfähigkeit konnte mittels entsprechender Wahl der elektrischen Schaltzeiten und -spannungen zielgerichtet manipuliert und geschalten werden. Es konnte darüber hinaus gezeigt werden, dass die hergestellten geladenen DW über eine Zeitspanne von mindestens zwei Monaten stabil sind und hierbei leitfähig bleiben. Die Leitfähigkeit der DW wurde weiterhin mittels Mikrowellenimpedanzmikroskopie untersucht. Dabei konnten DW-Leitfähigkeiten von 100 bis 1000 S/m für Mikrowellenfrequenzen von etwa 1GHz ermittelt werden.:1 INTRODUCTION 1 I THEORETICAL BASICS 5 2 FUNDAMENTALS 7 2.1 Ferroelectricity 7 2.1.1 Spontaneous polarization 8 2.1.2 Domains and domain walls 9 2.1.3 Charged domain walls 13 2.1.4 Conductive domain walls 16 2.2 Visualization of ferroelectric domains and domain walls 21 2.2.1 Light microscopy 22 2.2.2 Second-harmonic generation microscopy 22 2.2.3 Cherenkov second-harmonic generation microscopy 25 2.2.4 Optical coherence tomography 28 2.2.5 Piezo-response force microscopy 30 2.2.6 Ferroelectric lithography 31 2.2.7 Further methods 34 2.3 Lithium niobate and tantalate 37 2.3.1 General Properties 37 2.3.2 Stoichiometry 38 2.3.3 Optical properties 40 2.3.4 Intrinsic and extrinsic defects 43 2.3.5 Polarons 47 2.3.6 Ionic conductivity 51 3 METHODS 53 3.1 Sample Preparation 53 3.1.1 Poling stage 53 3.1.2 Thermal treatment 56 3.1.3 Ion slicing of LNO crystals 57 3.2 Atomic force microscopy 59 3.2.1 Non-contact and contact mode AFM microscopy 59 3.2.2 Piezo-response force microscopy (PFM) 60 3.2.3 Conductive atomic force microscopy (cAFM) 62 3.2.4 Scanning microwave impedance microscopy (sMIM) 63 3.2.5 AFM probes 66 3.3 Laser scanning microscope 67 3.4 Time-resolved luminescence spectroscopy 71 3.5 Energy-resolved photoelectron emission spectromicroscopy 72 II EXPERIMENTS 75 4 RESULTS 77 4.1 Three-dimensional profiling of domain walls 78 4.1.1 Randomly poled LNO and LTO domains 78 4.1.2 Periodically Poled Lithium Niobate 81 4.1.3 AFM-written Domains 83 4.1.4 Thermally treated LNO 84 4.1.5 Laser-written domains 86 4.2 Polarization charge textures 90 4.2.1 Random domains in Mg:LNO and Mg:LTO 90 4.2.2 Thermally-treated LNO 92 4.3 Quasi-phase matching SHG 92 4.4 Photoelectron microspectroscopy 97 4.5 Activated polaron transport 101 4.6 High voltage treated LNO 113 4.7 Conductive domain walls in exfoliated thin-film LNO 115 4.7.1 Conductance maps 116 4.7.2 Resistive switching by conductive domain walls 120 4.8 Microwave impedance microscopy 134 4.8.1 Finite-element method simulation 134 4.8.2 Scanning microwave impedance microscopy 136 5 conclusion & outlook 143 III EPILOGUE 147 a APPENDIX 149 a.1 Laser ablation dynamics on LNO surfaces 149 a.2 XPS across a conductive DW in LNO 150 a.3 XRD of thin-film exfoliated LNO 151 a.4 Domain writing in exfoliated thin-film LNO 152 a.5 Retention in conductance at DWs in thin-film exfoliated LNO 155 a.6 sMIM on DWs in thin-film exfoliated LNO 157 a.7 Domain inversion evolution under a tip by phase-field modeling 159 a.8 Current transients in exfoliated LNO 161 a.9 Surface acoustic wave excitation damping at DWs 162 a.10 Influence of UV illumination on domains in Mg:LNO 162 Acronyms 165 Symbols 169 List of figures 172 List of tables 176 Bibliography 177 Publications 225 Erklärung 23

18th IEEE Workshop on Nonlinear Dynamics of Electronic Systems: Proceedings

Proceedings of the 18th IEEE Workshop on Nonlinear Dynamics of Electronic Systems, which took place in Dresden, Germany, 26 – 28 May 2010.:Welcome Address ........................ Page I Table of Contents ........................ Page III Symposium Committees .............. Page IV Special Thanks ............................. Page V Conference program (incl. page numbers of papers) ................... Page VI Conference papers Invited talks ................................ Page 1 Regular Papers ........................... Page 14 Wednesday, May 26th, 2010 ......... Page 15 Thursday, May 27th, 2010 .......... Page 110 Friday, May 28th, 2010 ............... Page 210 Author index ............................... Page XII