Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Using a cognitive prosthesis to assist foodservice managerial decision-making

The artificial intelligence community has been notably unsuccessful in producing intelligent agents that think for themselves. However, there is an obvious need for increased information processing power in real life situations. An example of this can be witnessed in the training of a foodservice manager, who is expected to solve a wide variety of complex problems on a daily basis. This article explores the possibility of creating an intelligence aid, rather than an intelligence agent, to assist novice foodservice managers in making decisions that are congruent with a subject matter expert\u27s decision schema

Purposive Teaching Styles for Transdisciplinary AEC Education: A Diagnostic Learning Styles Questionnaire

With the progressive globalisation trend within the Architecture, Engineering, and Construction (AEC) industry, transdisciplinary education and training is widely acknowledged as being one of the key factors for leveraging AEC organisational success. Conventional education and training delivery approaches within AEC therefore need a paradigm shift in order to be able to address the emerging challenges of global practices. This study focuses on the use of Personalised Learning Environments (PLEs) to specifically address learners’ needs and preferences (learning styles) within managed Virtual Learning Environments (VLEs). This research posits that learners can learn better (and be more readily engaged in managed learning environments) with a bespoke PLE, in which the deployment of teaching and learning material is augmented towards their individual needs. In this respect, there is an exigent need for the Higher Educational Institutions (HEIs) to envelop these new approaches into their organisational learning strategy. However, part of this process requires decision-makers to fully understand the core nuances and interdependencies of functions and processes within the organisation, along with Critical Success Factors (CSFs) and barriers. This paper presents findings from the development of a holistic conceptual Diagnostic Learning Styles Questionnaire (DLSQ) Framework, comprised of six interrelated dependencies (i.e. Business Strategy, Pedagogy, Process, Resources, Systems Development, and Evaluation). These dependencies influence pedagogical effectiveness. These finding contribute additional understanding to the intrinsic nature of pedagogy in leveraging transdisciplinary AEC training within organisations (to improve learner effectiveness). This framework can help organisations augment and align their strategic priorities to learner-specific traits

Supporting Cyber-Physical Systems with Wireless Sensor Networks: An Outlook of Software and Services

Sensing, communication, computation and control technologies are the essential building blocks of a cyber-physical system (CPS). Wireless sensor networks (WSNs) are a way to support CPS as they provide fine-grained spatial-temporal sensing, communication and computation at a low premium of cost and power. In this article, we explore the fundamental concepts guiding the design and implementation of WSNs. We report the latest developments in WSN software and services for meeting existing requirements and newer demands; particularly in the areas of: operating system, simulator and emulator, programming abstraction, virtualization, IP-based communication and security, time and location, and network monitoring and management. We also reflect on the ongoing efforts in providing dependable assurances for WSN-driven CPS. Finally, we report on its applicability with a case-study on smart buildings

A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems

Recent technological advances have greatly improved the performance and features of embedded systems. With the number of just mobile devices now reaching nearly equal to the population of earth, embedded systems have truly become ubiquitous. These trends, however, have also made the task of managing their power consumption extremely challenging. In recent years, several techniques have been proposed to address this issue. In this paper, we survey the techniques for managing power consumption of embedded systems. We discuss the need of power management and provide a classification of the techniques on several important parameters to highlight their similarities and differences. This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded systems of tomorrow