7 research outputs found

    Algorithm-Architecture Co-Design for Digital Front-Ends in Mobile Receivers

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    The methodology behind this work has been to use the concept of algorithm-hardware co-design to achieve efficient solutions related to the digital front-end in mobile receivers. It has been shown that, by looking at algorithms and hardware architectures together, more efficient solutions can be found; i.e., efficient with respect to some design measure. In this thesis the main focus have been placed on two such parameters; first reduced complexity algorithms to lower energy consumptions at limited performance degradation, secondly to handle the increasing number of wireless standards that preferably should run on the same hardware platform. To be able to perform this task it is crucial to understand both sides of the table, i.e., both algorithms and concepts for wireless communication as well as the implications arising on the hardware architecture. It is easier to handle the high complexity by separating those disciplines in a way of layered abstraction. However, this representation is imperfect, since many interconnected "details" belonging to different layers are lost in the attempt of handling the complexity. This results in poor implementations and the design of mobile terminals is no exception. Wireless communication standards are often designed based on mathematical algorithms with theoretical boundaries, with few considerations to actual implementation constraints such as, energy consumption, silicon area, etc. This thesis does not try to remove the layer abstraction model, given its undeniable advantages, but rather uses those cross-layer "details" that went missing during the abstraction. This is done in three manners: In the first part, the cross-layer optimization is carried out from the algorithm perspective. Important circuit design parameters, such as quantization are taken into consideration when designing the algorithm for OFDM symbol timing, CFO, and SNR estimation with a single bit, namely, the Sign-Bit. Proof-of-concept circuits were fabricated and showed high potential for low-end receivers. In the second part, the cross-layer optimization is accomplished from the opposite side, i.e., the hardware-architectural side. A SDR architecture is known for its flexibility and scalability over many applications. In this work a filtering application is mapped into software instructions in the SDR architecture in order to make filtering-specific modules redundant, and thus, save silicon area. In the third and last part, the optimization is done from an intermediate point within the algorithm-architecture spectrum. Here, a heterogeneous architecture with a combination of highly efficient and highly flexible modules is used to accomplish initial synchronization in at least two concurrent OFDM standards. A demonstrator was build capable of performing synchronization in any two standards, including LTE, WiFi, and DVB-H

    Synchronization in all-digital QAM receivers

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    The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective and economical alternative to the design of Application Specific Integrated Circuits (ASICs). The primary reasons for switching to FPGAs are lower development and non-recurring engineering costs, the flexibility to design to a preliminary standard and adapt the design as the standard evolves, as well as the option of performing software updates in the field. A sector with strong interest in FPGAs is the coaxial cable TV/Internet distribution industry. The creation of soft preliminary standards by the standards organization governing the industry has been the main catalyst for the massive adoption of FPGAs by small to medium size companies, which see this technology as an opportunity to compete in this open market. Both the circuit speed and the economy of FPGA technology depend upon using algorithms that map efficiently into its fabric. Often it is prudent to sacrifice performance to improve either clock speed or economy when developing with FPGAs. The purpose of this research is to both revise and devise synchronization algorithms / structures for cable digital receivers that are to be implemented in FPGA. The main communication scheme used by the coaxial cable distribution industry is digital Quadrature Amplitude Modulation (QAM). The problem of synchronizing to the QAM signal in the receiver is not a new topic and several synchronization-related circuits, which were devised with ASICs implementation in mind, can be found in the open literature. Of interest in this thesis is the non-data-aided digital timing synchronizer that was proposed by D'Andrea to recover timing with no knowledge of the transmitted data. Accurate timing estimation was achieved by reshaping the received signal with a prefilter prior to estimating the timing. A problem with D'Andrea's synchronizer is that the prefilter for reshaping the signal is a relatively long Finite Impulse Response (FIR) filter, whose implementation requires a large number of multipliers. This may not have been an issue with ASICs in as much as the number of hardwired multipliers on a chip is not limited as it is in an FPGA chip. One contribution in this research is to propose an alternative to D'Andrea's synchronizer by replacing the long FIR filter with two single-pole Infinite Impulse Response (IIR) filters that are directly placed inside the timing recovery loop. This novel architecture, which drastically reduces the number of multipliers, is well suited for FPGA implementation. Non-data-aided feedforward synchronizers, which use the same prefilter as D'Andrea's synchronizer, have been receiving significant attention in recent years. Detailed performance analysis for these synchronizers can be found in the open literature. These synchronizers have the advantage of using a feedfordward structure rather than a feedback structure, as it is the case in D'Andrea's synchronizer, to estimate the timing. While D'Andrea's synchronizer has an advantage in performance over a non-data-aided feedforward synchronizer, this has not been reported in the literature. In this thesis a second contribution consists of thoroughly analyzing the steady state timing jitter in D'Andrea synchronizer by deriving a closed-form expression for the noise power spectrum and a simple equation to estimate the timing jitter variance. A third contribution is a novel low-complexity and fast acquisition coherent detector for the detection of Quadrature Phase Shift Keying (QPSK) (i.e., 4-QAM) symbols. This detector performs carrier phase synchronization much faster than a conventional coherent detector. The acquisition time is comparable to that of a differential detector. The fast acquisition comes at the expense of phase jitter, and the end result is a 1 dB performance loss over theoretical coherent detection. This detector can be used in place of the differential detector with no economic penalty. Doing so yields a performance advantage of about 2 dB over differential detection

    Enhanced coding, clock recovery and detection for a magnetic credit card

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    Merged with duplicate record 10026.1/2299 on 03.04.2017 by CS (TIS)This thesis describes the background, investigation and construction of a system for storing data on the magnetic stripe of a standard three-inch plastic credit in: inch card. Investigation shows that the information storage limit within a 3.375 in by 0.11 in rectangle of the stripe is bounded to about 20 kBytes. Practical issues limit the data storage to around 300 Bytes with a low raw error rate: a four-fold density increase over the standard. Removal of the timing jitter (that is prob-' ably caused by the magnetic medium particle size) would increase the limit to 1500 Bytes with no other system changes. This is enough capacity for either a small digital passport photograph or a digitized signature: making it possible to remove printed versions from the surface of the card. To achieve even these modest gains has required the development of a new variable rate code that is more resilient to timing errors than other codes in its efficiency class. The tabulation of the effects of timing errors required the construction of a new code metric and self-recovering decoders. In addition, a new method of timing recovery, based on the signal 'snatches' has been invented to increase the rapidity with which a Bayesian decoder can track the changing velocity of a hand-swiped card. The timing recovery and Bayesian detector have been integrated into one computation (software) unit that is self-contained and can decode a general class of (d, k) constrained codes. Additionally, the unit has a signal truncation mechanism to alleviate some of the effects of non-linear distortion that are present when a magnetic card is read with a magneto-resistive magnetic sensor that has been driven beyond its bias magnetization. While the storage density is low and the total storage capacity is meagre in comparison with contemporary storage devices, the high density card may still have a niche role to play in society. Nevertheless, in the face of the Smart card its long term outlook is uncertain. However, several areas of coding and detection under short-duration extreme conditions have brought new decoding methods to light. The scope of these methods is not limited just to the credit card

    Traitement du signal pour les communications numériques au travers de canaux radio-mobiles

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    This manuscript of ''Habilitation à diriger les Recherches'' (Habilitation to conduct researches) gives me the opportunity to take stock of the last 14 years on my associate professor activities and on my research works in the field of signal processing for digital communications, particularly for radio-mobile communications. The purpose of this signal processing is generally to obtain a robust transmission, despite the passage of digital information through a communication channel disrupted by the mobility between the transmitter and the receiver (Doppler effect), the phenomenon of echoes (multi-path propagation), the addition of noise or interference, or by limitations in bandwidth, in transmitted power or in signal-to-noise ratio. In order to recover properly the digital information, the receiver needs in general to have an accurate knowledge of the channel state. Much of my work has focused on receiver synchronization or more generally on the dynamic estimation of the channel parameters (delays, phases, amplitudes, Doppler shifts, ...). We have developed estimators and studied their performance in asymptotic variance, and have compared them to minimum lower bound (Cramer-rao or Bayesian Cramer Rao bounds). Some other studies have focused only on the recovering of information (''detection'' or ''equalization'' task) by the receiver after channel estimation, or proposed and analyzed emission / reception schemes, reliable for certain scenarios (transmit diversity scheme for flat fading channel, scheme with high energy efficiency, ...).Ce mémoire de HDR est l'occasion de dresser un bilan des 14 dernières années concernant mes activités d'enseignant-chercheur et mes travaux de recherche dans le domaine du traitement du signal pour les communications numériques, et plus particulièrement les communications radio-mobiles. L'objet de ce traitement du signal est globalement l'obtention d'une transmission robuste, malgré le passage de l'information numérique au travers d'un canal de communication perturbé par la mobilité entre l'émetteur et le récepteur (effet Doppler), le phénomène d'échos, l'addition de bruit ou d'interférence, ou encore par des limitations en bande-passante, en puissance transmise ou en rapport-signal à bruit. Afin de restituer au mieux l'information numérique, le récepteur a en général besoin de disposer d'une connaissance précise du canal. Une grande partie de mes travaux s'est intéressé à l'estimation dynamique des paramètres de ce canal (retards, phases, amplitudes, décalages Doppler, ...), et en particulier à la synchronisation du récepteur. Quelques autres travaux se sont intéressés seulement à la restitution de l'information (tâches de ''détection'' ou d' ''égalisation'') par le récepteur une fois le canal estimé, ou à des schémas d'émission / réception spécifiques. La synthèse des travaux commence par une introduction générale décrivant les ''canaux de communications'' et leurs problèmes potentiels, et positionne chacun de mes travaux en ces termes. Une première partie s'intéresse aux techniques de réception pour les signaux à spectre étalé des systèmes d'accès multiple à répartition par codes (CDMA). Ces systèmes large-bande offrent un fort pouvoir de résolution temporelle et des degrés de liberté, que nous avons exploités pour étudier l'égalisation et la synchronisation (de retard et de phase) en présence de trajets multiples et d'utilisateurs multiples. La première partie regroupe aussi d'autres schémas d'émission/réception, proposés pour leur robustesse dans différents scénarios (schéma à diversité pour canaux à évanouissement plats, schéma à forte efficacité énergétique, ...). La seconde partie est consacrée à l'estimation dynamique Bayésienne des paramètres du canal. On suppose ici qu'une partie des paramètres à estimer exhibe des variations temporelles aléatoires selon une certaine loi à priori. Nous proposons d'abord des estimateurs et des bornes minimales d'estimation pour des modèles de transmission relativement complexes, en raison de la distorsion temporelle due à la forte mobilité en modulation multi-porteuse (OFDM), ou de la présence de plusieurs paramètres à estimer conjointement, ou encore de non linéarités dans les modèles. Nous nous focalisons ensuite sur le problème d'estimation des amplitudes complexes des trajets d'un canal à évolution lente (à 1 ou plusieurs bonds). Nous proposons des estimateurs récursifs (dénommés CATL, pour ''Complex Amplitude Tracking Loop'') à structure imposée inspirée par les boucles à verrouillage de phase numériques, de performance asymptotiques proches des bornes minimales. Les formules analytiques approchées de performances asymptotiques et de réglages de ces estimateurs sont établies sous forme de simples fonctions des paramètres physiques (spectre Doppler, retards, niveau de bruit). Puis étant donné les liens établis entre ces estimateurs CATL et certains filtres de Kalman (construits pour des modèles d'état de type marche aléatoire intégrée), les formules approchées de performances asymptotiques et de réglage de ces filtres de Kalman sont aussi dérivées

    Efficient algorithms for arbitrary sample rate conversion with application to wave field synthesis

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    Arbitrary sample rate conversion (ASRC) is used in many fields of digital signal processing to alter the sampling rate of discrete-time signals by arbitrary, potentially time-varying ratios. This thesis investigates efficient algorithms for ASRC and proposes several improvements. First, closed-form descriptions for the modified Farrow structure and Lagrange interpolators are derived that are directly applicable to algorithm design and analysis. Second, efficient implementation structures for ASRC algorithms are investigated. Third, this thesis considers coefficient design methods that are optimal for a selectable error norm and optional design constraints. Finally, the performance of different algorithms is compared for several performance metrics. This enables the selection of ASRC algorithms that meet the requirements of an application with minimal complexity. Wave field synthesis (WFS), a high-quality spatial sound reproduction technique, is the main application considered in this work. For WFS, sophisticated ASRC algorithms improve the quality of moving sound sources. However, the improvements proposed in this thesis are not limited to WFS, but applicable to general-purpose ASRC problems.Verfahren zur unbeschränkten Abtastratenwandlung (arbitrary sample rate conversion,ASRC) ermöglichen die Änderung der Abtastrate zeitdiskreter Signale um beliebige, zeitvarianteVerhältnisse. ASRC wird in vielen Anwendungen digitaler Signalverarbeitung eingesetzt.In dieser Arbeit wird die Verwendung von ASRC-Verfahren in der Wellenfeldsynthese(WFS), einem Verfahren zur hochqualitativen, räumlich korrekten Audio-Wiedergabe, untersucht.Durch ASRC-Algorithmen kann die Wiedergabequalität bewegter Schallquellenin WFS deutlich verbessert werden. Durch die hohe Zahl der in einem WFS-Wiedergabesystembenötigten simultanen ASRC-Operationen ist eine direkte Anwendung hochwertigerAlgorithmen jedoch meist nicht möglich.Zur Lösung dieses Problems werden verschiedene Beiträge vorgestellt. Die Komplexitätder WFS-Signalverarbeitung wird durch eine geeignete Partitionierung der ASRC-Algorithmensignifikant reduziert, welche eine effiziente Wiederverwendung von Zwischenergebnissenermöglicht. Dies erlaubt den Einsatz hochqualitativer Algorithmen zur Abtastratenwandlungmit einer Komplexität, die mit der Anwendung einfacher konventioneller ASRCAlgorithmenvergleichbar ist. Dieses Partitionierungsschema stellt jedoch auch zusätzlicheAnforderungen an ASRC-Algorithmen und erfordert Abwägungen zwischen Performance-Maßen wie der algorithmischen Komplexität, Speicherbedarf oder -bandbreite.Zur Verbesserung von Algorithmen und Implementierungsstrukturen für ASRC werdenverschiedene Maßnahmen vorgeschlagen. Zum Einen werden geschlossene, analytischeBeschreibungen für den kontinuierlichen Frequenzgang verschiedener Klassen von ASRCStruktureneingeführt. Insbesondere für Lagrange-Interpolatoren, die modifizierte Farrow-Struktur sowie Kombinationen aus Überabtastung und zeitkontinuierlichen Resampling-Funktionen werden kompakte Darstellungen hergeleitet, die sowohl Aufschluss über dasVerhalten dieser Filter geben als auch eine direkte Verwendung in Design-Methoden ermöglichen.Einen zweiten Schwerpunkt bildet das Koeffizientendesign für diese Strukturen, insbesonderezum optimalen Entwurf bezüglich einer gewählten Fehlernorm und optionaler Entwurfsbedingungenund -restriktionen. Im Gegensatz zu bisherigen Ansätzen werden solcheoptimalen Entwurfsmethoden auch für mehrstufige ASRC-Strukturen, welche ganzzahligeÜberabtastung mit zeitkontinuierlichen Resampling-Funktionen verbinden, vorgestellt.Für diese Klasse von Strukturen wird eine Reihe angepasster Resampling-Funktionen vorgeschlagen,welche in Verbindung mit den entwickelten optimalen Entwurfsmethoden signifikanteQualitätssteigerungen ermöglichen.Die Vielzahl von ASRC-Strukturen sowie deren Design-Parameter bildet eine Hauptschwierigkeitbei der Auswahl eines für eine gegebene Anwendung geeigneten Verfahrens.Evaluation und Performance-Vergleiche bilden daher einen dritten Schwerpunkt. Dazu wirdzum Einen der Einfluss verschiedener Entwurfsparameter auf die erzielbare Qualität vonASRC-Algorithmen untersucht. Zum Anderen wird der benötigte Aufwand bezüglich verschiedenerPerformance-Metriken in Abhängigkeit von Design-Qualität dargestellt.Auf diese Weise sind die Ergebnisse dieser Arbeit nicht auf WFS beschränkt, sondernsind in einer Vielzahl von Anwendungen unbeschränkter Abtastratenwandlung nutzbar
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