Jitter and phase noise in ring oscillators

A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed

Analysis of Phase Noise and Jitter in Ring Oscillators

Voltage controlled oscillators (VCOs) have gain paramount importance in frequency modulation (FM) and pulse modulation (PM) circuits, phase locked loops (PLLs), function generators, frequency synthesizers etc. which are vital for communication circuits. CMOS based ring oscillators have tuning range, tuning gain and phase noise as the important characteristics. The most difficult task is that variation of phase due to stochastic perturbations. Phase noise has been the designer’s primary concerned. The effect of oscillator’s noise is one of the most insightful issues in the designing of modern RF telecommunication systems. A low phase noise with minimum power dissipation is rapidly preferred criteria for the design of voltage controlled ring oscillators (VCROs). A very simple and precise analysis of different phase noise models of ring VCOs and their causes is analyzed in this paper. For each case, the flicker noise and the white noise component of phase noise and jitter are considered which limits the signal. The important elements that determine the phase noise in VCOs are the transistor's flicker noise ( noise), the output power level, and the quality factor (Q). A synchronized relationship among the effective noise components in the oscillatory circuits leads to good agreement for new design insights and also improves the performance. Keywords: Ring Oscillators, Voltage Controlled Oscillator, Voltage Controlled Ring Oscillator, Phase noise, jitter

Oscillator phase noise: a tutorial

Linear time-invariant (LTI) phase noise theories provide important qualitative design insights but are limited in their quantitative predictive power. Part of the difficulty is that device noise undergoes multiple frequency translations to become oscillator phase noise. A quantitative understanding of this process requires abandoning the principle of time invariance assumed in most older theories of phase noise. Fortunately, the noise-to-phase transfer function of oscillators is still linear, despite the existence of the nonlinearities necessary for amplitude stabilization. In addition to providing a quantitative reconciliation between theory and measurement, the time-varying phase noise model presented in this tutorial identifies the importance of symmetry in suppressing the upconversion of 1/f noise into close-in phase noise, and provides an explicit appreciation of cyclostationary effects and AM-PM conversion. These insights allow a reinterpretation of why the Colpitts oscillator exhibits good performance, and suggest new oscillator topologies. Tuned LC and ring oscillator circuit examples are presented to reinforce the theoretical considerations developed. Simulation issues and the accommodation of amplitude noise are considered in appendixes

Reduction of 1/f Noise in MOSFETS by Switched Bias Techniques

Switched Biasing is presented as a technique for reducing the 1/f noise in MOSFETS. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its 1/f noise!! The history of the discovery of the effect and the main experimental results obtained so far will be reviewed

A 12MHz Switched-Capacitor Relaxation Oscillator with a Nearly Minimal FoM of -161dBc/Hz

In this work the phase noise performance of relaxation oscillators has been analyzed resulting in simple though precise phase noise expressions. These expressions have lead to a new relaxation oscillator topology, which exploits a noise filtering technique implemented with a switched-capacitor circuit to minimize phase noise. Measurements on a 65nm CMOS design show a sawtooth waveform, a frequency tuning range between 1 and 12MHz and a rather constant frequency tuning gain. At 12MHz oscillation frequency it consumes 90μW while the phase noise is -109dBc/Hz at 100KHz offset frequency. By minimizing and balancing noise contributions of charge and discharge mechanisms, a nearly minimal FoM of -161dBc/Hz has been achieved, which is a 6dB improvement over state-of-the-art

A 90μW 12MHz Relaxation Oscillator with a -162dB FOM

A relaxation oscillator exploits a noise filtering technique implemented with a switched-capacitor circuit to minimize phase noise. A 65nm CMOS design produces a sawtooth waveform, has a frequency tuning range of 1 to 12MHz and a constant frequency-tuning gain. By minimizing and balancing noise contributions from charge and discharge mechanisms, a FOM of -162dB is achieved, which is a 7dB improvement over state-of-the-art

A general theory of phase noise in electrical oscillators

A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed

Jitter decomposition in ring oscillators

Abstract — It is important to separate random jitter from de-terministic jitter to quantify their contributions to the total jit-ter. This paper identifies the limitations of the existing method-ologies for jitter decomposition, and develops a new and efficient approach using time lag correlation functions to decompose dif-ferent jitter components. The theory of the approach is developed and it is applied to a ring oscillator simulated in a 0.6-um AMI CMOS process. Results show good agreement between the theory and hspice simulation. I

Prediction of phase noise and jitter in ring oscillators

This thesis presents distinctly different methods of accurately predicting phase noise and absolute jitter in ring oscillators. The phase noise prediction methods are the commercially available SpectreRF and isf_tool, a simulator developed in this work from the Hajimiri and Lee theory of phase noise. Absolute jitter due to deterministic supply and substrate noise is predicted by Spectre time domain simulations and equations developed that can predict the absolute jitter due to a sinusoidal noise source at any frequency. These jitter prediction methods show that ring oscillator circuits respond differently to deterministic noise that is injected symmetrically versus noise that is injected asymmetrically, and a new jitter metric, peak jitter, is developed in this work to characterize absolute jitter caused by deterministic noise sources. These prediction methods are validated with measurements from two test chips with a combined 18 oscillators and 5 distinct architectures, and both are fabricated in the TSMC 0.35μm process. Each prediction method is shown to be consistent with over 2500 phase noise measurements taken from 10 oscillators and 5 architectures and over 1200 absolute jitter measurements due to sinusoidal supply and substrate noise taken from 11 oscillators and 3 architectures