Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

Gain and time resolution of 45 μ\mum thin Low Gain Avalanche Detectors before and after irradiation up to a fluence of 101510^{15} neq_{eq}/cm2^2

Low Gain Avalanche Detectors (LGADs) are silicon sensors with a built-in charge multiplication layer providing a gain of typically 10 to 50. Due to the combination of high signal-to-noise ratio and short rise time, thin LGADs provide good time resolutions. LGADs with an active thickness of about 45 $\mu$m were produced at CNM Barcelona. Their gains and time resolutions were studied in beam tests for two different multiplication layer implantation doses, as well as before and after irradiation with neutrons up to $10^{15}$ n$_{eq}$/cm$^2$. The gain showed the expected decrease at a fixed voltage for a lower initial implantation dose, as well as for a higher fluence due to effective acceptor removal in the multiplication layer. Time resolutions below 30 ps were obtained at the highest applied voltages for both implantation doses before irradiation. Also after an intermediate fluence of $3\times10^{14}$ n$_{eq}$/cm$^2$, similar values were measured since a higher applicable reverse bias voltage could recover most of the pre-irradiation gain. At $10^{15}$ n$_{eq}$/cm$^2$, the time resolution at the maximum applicable voltage of 620 V during the beam test was measured to be 57 ps since the voltage stability was not good enough to compensate for the gain layer loss. The time resolutions were found to follow approximately a universal function of gain for all implantation doses and fluences.Comment: 17 page

An Ultra-Low-Power Track-and-Hold Amplifier

The future of electronics is the Internet of Things (IoT) paradigm, where always-on devices and sensors monitor and transform everyday life. A plethora of applications (such as navigating drivers past road hazards or monitoring bridge and building stresses) employ this technology. These unattended ground-sensor applications require decade(s)-long operational life-times without battery changes. Such electronics demand stringent performance specifications with only nano-Watt power levels.This thesis presents an ultra-low-power track-and-hold amplifier for such systems. It serves as the front-end of a SAR-ADC or the building block for equalizers or filters. This amplifier\u27s design attains exceptional hold times by mitigating switch subthreshold leakage and bulk leakage. Its novel transmission-gate topology achieves wide-swing performance. Though only consuming 100 pico-Watts, it achieves a precision of 7.6 effective number of bits (ENOB). The track-and-hold amplifier was designed in 130-nm CMOS

Calibrating and Stabilizing Spectropolarimeters with Charge Shuffling and Daytime Sky Measurements

Well-calibrated spectropolarimetry studies at resolutions of $R>$10,000 with signal-to-noise ratios (SNRs) better than 0.01\% across individual line profiles, are becoming common with larger aperture telescopes. Spectropolarimetric studies require high SNR observations and are often limited by instrument systematic errors. As an example, fiber-fed spectropolarimeters combined with advanced line-combination algorithms can reach statistical error limits of 0.001\% in measurements of spectral line profiles referenced to the continuum. Calibration of such observations is often required both for cross-talk and for continuum polarization. This is not straightforward since telescope cross-talk errors are rarely less than $\sim$1\%. In solar instruments like the Daniel K. Inouye Solar Telescope (DKIST), much more stringent calibration is required and the telescope optical design contains substantial intrinsic polarization artifacts. This paper describes some generally useful techniques we have applied to the HiVIS spectropolarimeter at the 3.7m AEOS telescope on Haleakala. HiVIS now yields accurate polarized spectral line profiles that are shot-noise limited to 0.01\% SNR levels at our full spectral resolution of 10,000 at spectral sampling of $\sim$100,000. We show line profiles with absolute spectropolarimetric calibration for cross-talk and continuum polarization in a system with polarization cross-talk levels of essentially 100\%. In these data the continuum polarization can be recovered to one percent accuracy because of synchronized charge-shuffling model now working with our CCD detector. These techniques can be applied to other spectropolarimeters on other telescopes for both night and day-time applications such as DKIST, TMT and ELT which have folded non-axially symmetric foci.Comment: Accepted to A&

A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2

This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 m

Design of a low power switched-capacitor pipeline analog-to-digital converter

An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious. In this thesis, several novel designs used to improve ADCs operation speed and reduce ADC power consumption are proposed. First, a high speed switched source follower (SSF) sample and hold amplifier without feedthrough penalty is implemented and simulated. The SSF sample and hold amplifier can achieve 6 Bit resolution with sampling rate at 10Gs/s. Second, a novel rail-to-rail time domain comparator used in successive approximation register ADC (SAR ADC) is implemented and simulated. The simulation results show that the proposed SAR ADC can only consume 1.3 muW with a 0.7 V power supply. Finally, a prototype pipeline ADC is implemented and fabricated in an IBM 90nm CMOS process. The proposed design is validated using measurement on a fabricated silicon IC, and the proposed 10-bit ADC achieves a peak signal-to-noise- and-distortion-ratio (SNDR) of 47 dB. This SNDR translates to a figure of merit (FOM) of 2.6N/conversion-step with a 1.2 V power supply

Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ

Pipelined analog-to-digital conversion using current-mode reference shifting

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresPipeline Analog-to-digital converters (ADCs) are the most popular architecture for high-speed medium-to-high resolution applications. A fundamental, but often unreferenced building block of pipeline ADCs are the reference voltage circuits. They are required to maintain a stable reference with low output impedance to drive large internal switched capacitor loads quickly. Achieving this usually leads to a scheme that consumes a large portion of the overall power and area. A review of the literature shows that the required stable reference can be achieved with either on-chip buffering or with large off-chip decoupling capacitors. On-chip buffering is ideal for system integration but requires a high speed buffer with high power dissipation. The use of a reference with off-chip decoupling results in significant power savings but increases the pads of chip, the count of external components and the overall system cost. Moreover the amount of ringing on the internal reference voltage caused by the series inductance of the package makes this solution not viable for high speed ADCs. To address this challenge, a pipeline ADC employing a multiplying digital-to-analog converter (MDAC) with current-mode reference shifting is presented. Consequently, no reference voltages and, therefore, no voltage buffers are necessary. The bias currents are generated on-chip by a reference current generator that dissipates low power. The proposed ADC is designed in a 65 nm CMOS technology and operates at sampling rates ranging from 10 to 80 MS/s. At 40 MS/s the ADC dissipates 10.8 mW from a 1.2 V power supply and achieves an SNDR of 57.2 dB and a THD of -68 dB, corresponding to an ENOB of 9.2 bit. The corresponding figure of merit is 460 fJ/step