최적 위상 검출 회로를 이용한 클럭 및 데이터 복원 회로에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 8. 김재하.Bang-bang phase detectors are widely used for today's high-speed communication circuits such as phase-locked loops (PLLs), delay-locked loops (DLLs) and clock-and-data recovery loops (CDRs) because it is simple, fast, accurate and amenable to digital implementations. However, its hard nonlinearity poses difficulties in design and analyses of the bang-bang controlled timing loops. Especially, dithering in bang-bang controlled CDRs sets conflicting requirements on the phase adjustment resolution as one tries to maximize the tracking bandwidth and minimize jitter. A fine phase step is helpful to minimize the dithering, but it requires circuits with finer resolution that consumes large power and area. In this background, this dissertation introduces an optimal phase detection technique that can minimize the effect of dithering without requiring fine phase resolution. A novel phase interval detector that looks for a phase interval enclosing the desired lock point is shown to find the optimal phase that minimizes the timing error without dithering. A digitally-controlled, phase-interpolating DLL-based CDR fabricated in 65nm CMOS demonstrates that it can achieve small area of 0.026mm^2 and low jitter of 41mUIp-p with a coarse phase adjustment step of 0.11UI, while dissipating only 8.4mW at 5Gbps. For the theoretic basis, various analysis techniques to understand bang-bang controlled timing loops are also presented. The proposed techniques are explained for both linearized loop and non-linear one, and applied to the evaluation of the proposed phase detection technique.1 Introduction 1 1.1 Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Contribution and Organization . . . . . . . . . . . . . . . . . 6 2 Pseudo-Linear Analysis of Bang-Bang Controlled Loops 9 2.1 Model of a Second-Order, Bang-Bang Controlled Timing Loop . . . 9 2.2 Necessary Condition for the Pseudo-Linear Analysis . . . . . . . . . 12 2.3 Derivation of Necessity Condition for the Pseudo-Linear Analysis . . 17 2.4 A Linearized Model of the Bang-Bang Phase Detector . . . . . . . . 18 2.5 Linearized Gain of a Bang-Bang Phase Detector for Jitter Transfer and Jitter Generation Analyses . . . . . . . . . . . . . . . . . . . . . 21 2.6 Jitter Transfer and Jitter Generation Analyses . . . . . . . . . . . . 29 2.7 Linearized Gains of a Bang-bang Phase Detector for Jitter Tolerance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8 Jitter Tolerance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 41 3 Nonlinear Analysis of Bang-Bang Controlled Loops 48 3.1 Transient Analysis of Bang-Bang Controlled Timing Loops . . . . . 48 3.2 Phase-portrait Analysis of Bang-Bang Controlled Timing Loops . . . 51 3.3 Markov-chain Analysis of Bang-Bang Controlled Timing Loops . . . 53 3.4 Analysis of Clock-and-Data Recovery Circuits . . . . . . . . . . . . . 57 3.4.1 Prediction of Bit-Error Rate . . . . . . . . . . . . . . . . . . 57 3.4.2 Eect of Transition Density . . . . . . . . . . . . . . . . . . . 58 3.4.3 Eect of Decimation . . . . . . . . . . . . . . . . . . . . . . . 61 3.4.4 Analysis of Oversampling Phase Detectors . . . . . . . . . . . 66 4 Design of Ditherless Clock and Data Recovery Circuit 75 4.1 Optimal Phase Detection . . . . . . . . . . . . . . . . . . . . . . . . 75 4.2 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.3 Analysis of the CDR with Phase Interval Detection . . . . . . . . . . 84 4.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.4.1 Sampling Receiver . . . . . . . . . . . . . . . . . . . . . . . . 89 4.4.2 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.4.3 Digital Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . 95 4.4.4 Phase Locked-Loop . . . . . . . . . . . . . . . . . . . . . . . . 98 4.4.5 Phase Interpolator . . . . . . . . . . . . . . . . . . . . . . . . 99 4.5 Built-In Self-Test Circuit for Jitter Tolerance Measurement . . . . . 102 4.6 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5 Conclusion 114 References 116Docto

Jitter Tolerance Analysis of Clock and Data Recovery Circuits using Matlab and VHDL-AMS

In the scope of the development of a complete top-down design flow targeting clock and data recovery circuits for high-speed data links, we present two methods to analyze the jitter tolerance of such links, based on statistical simulation of incoming data jitter and its effects on the recovered data bit error rate using Matlab. The second method is based on time-domain simulation using VHDL and VHDL-AMS, where the bit-error rate is estimated based on the eye opening in the eye diagram

In-system Jitter Measurement Based on Blind Oversampling Data Recovery

The paper describes a novel method for simple estimation of jitter contained in a received digital signal. The main objective of our research was to enable a non-invasive measurement of data link properties during a regular data transmission. To evaluate the signal quality we estimate amount of jitter contained in the received signal by utilizing internal signals of a data recovery circuit. The method is a pure digital algorithm suitable for implementation in any digital integrated circuit (ASIC or FPGA). It is based on a blind-oversampling data recovery circuit which is used in some receivers instead of a traditional PLL-based clock and data recovery (CDR) circuit. Combination of the described jitter measurement block and the data recovery block forms a very efficient input part of the digital receiver. In such configuration it is able to simultaneously perform both data communication (data recovery) and signal quality estimation (jitter measurement). The jitter measurement portion of the receiver requires no special connection of the received data signal. Thus the measured signal is not influenced by the measurement circuitry at all. To verify the method we performed a measurement on a laboratory free-space optics link. Results of the measurement are satisfactory and can be used for on-line channel analysis

10Gb/s Bang-Bang Clock and Data Recovery (CDR) for optical transmission systems

A Bang-Bang Clock-Data Recovery (CDR) for 10Gb/s optical transmission systems is presented. A direct modulated architecture is used for the design. Its loop characteristics can be derived using an analogy to Σ Δ theory. The circuit was produced and measured in a commercial 0.25μm BiCMOS technology with a transition frequency <i>f</i>_<i>T</i>70=GHz

통계적 주파수 검출기 기반 기준 주파수를 사용하지 않는 클록 및 데이터 복원 회로의 설계 방법론

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.In this thesis, a design of a high-speed, power-efficient, wide-range clock and data recovery (CDR) without a reference clock is proposed. A frequency acquisition scheme using a stochastic frequency detector (SFD) based on the Alexander phase detector (PD) is utilized for the referenceless operation. Pat-tern histogram analysis is presented to analyze the frequency acquisition behavior of the SFD and verified by simulation. Based on the information obtained by pattern histogram analysis, SFD using autocovariance is proposed. With a direct-proportional path and a digital integral path, the proposed referenceless CDR achieves frequency lock at all measurable conditions, and the measured frequency acquisition time is within 7μs. The prototype chip has been fabricated in a 40-nm CMOS process and occupies an active area of 0.032 mm2. The proposed referenceless CDR achieves the BER of less than 10-12 at 32 Gb/s and exhibits an energy efficiency of 1.15 pJ/b at 32 Gb/s with a 1.0 V supply.본 논문은 기준 클럭이 없는 고속, 저전력, 광대역으로 동작하는 클럭 및 데이터 복원회로의 설계를 제안한다. 기준 클럭이 없는 동작을 위해서 알렉산더 위상 검출기에 기반한 통계적 주파수 검출기를 사용하는 주파수 획득 방식이 사용된다. 통계적 주파수 검출기의 주파수 추적 양상을 분석하기 위해 패턴 히스토그램 분석 방법론을 제시하였고 시뮬레이션을 통해 검증하였다. 패턴 히스토그램 분석을 통해 얻은 정보를 바탕으로 자기공분산을 이용한 통계적 주파수 검출기를 제안한다. 직접 비례 경로와 디지털 적분 경로를 통해 제안된 기준 클럭이 없는 클럭 및 데이터 복원회로는 모든 측정 가능한 조건에서 주파수 잠금을 달성하는 데 성공하였고, 모든 경우에서 측정된 주파수 추적 시간은 7μs 이내이다. 40-nm CMOS 공정을 이용하여 만들어진 칩은 0.032 mm2의 면적을 차지한다. 제안하는 클럭 및 데이터 복원회로는 32 Gb/s의 속도에서 비트에러율 10-12 이하로 동작하였고, 에너지 효율은 32Gb/s의 속도에서 1.0V 공급전압을 사용하여 1.15 pJ/b을 달성하였다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 13 CHAPTER 2 BACKGROUNDS 14 2.1 CLOCKING ARCHITECTURES IN SERIAL LINK INTERFACE 14 2.2 GENERAL CONSIDERATIONS FOR CLOCK AND DATA RECOVERY 24 2.2.1 OVERVIEW 24 2.2.2 JITTER 26 2.2.3 CDR JITTER CHARACTERISTICS 33 2.3 CDR ARCHITECTURES 39 2.3.1 PLL-BASED CDR – WITH EXTERNAL REFERENCE CLOCK 39 2.3.2 DLL/PI-BASED CDR 44 2.3.3 PLL-BASED CDR – WITHOUT EXTERNAL REFERENCE CLOCK 47 2.4 FREQUENCY ACQUISITION SCHEME 50 2.4.1 TYPICAL FREQUENCY DETECTORS 50 2.4.1.1 DIGITAL QUADRICORRELATOR FREQUENCY DETECTOR 50 2.4.1.2 ROTATIONAL FREQUENCY DETECTOR 54 2.4.2 PRIOR WORKS 56 CHAPTER 3 DESIGN OF THE REFERENCELESS CDR USING SFD 58 3.1 OVERVIEW 58 3.2 PROPOSED FREQUENCY DETECTOR 62 3.2.1 MOTIVATION 62 3.2.2 PATTERN HISTOGRAM ANALYSIS 68 3.2.3 INTRODUCTION OF AUTOCOVARIANCE TO STOCHASTIC FREQUENCY DETECTOR 75 3.3 CIRCUIT IMPLEMENTATION 83 3.3.1 IMPLEMENTATION OF THE PROPOSED REFERENCELESS CDR 83 3.3.2 CONTINUOUS-TIME LINEAR EQUALIZER (CTLE) 85 3.3.3 DIGITALLY-CONTROLLED OSCILLATOR (DCO) 87 3.4 MEASUREMENT RESULTS 89 CHAPTER 4 CONCLUSION 99 APPENDIX A DETAILED FREQUENCY ACQUISITION WAVEFORMS OF THE PROPOSED SFD 100 BIBLIOGRAPHY 108 초 록 122박

The truth about 2-level transition elimination in bang-bang PAM-4 CDRs

Reception of 4-level pulse amplitude modulation (PAM-4) requires a clock and data recovery (CDR) circuit, typically implemented by a PLL-like structure. An essential block in such a CDR is the phase detector which should detect whether the recovered clock leads or lags the incoming data edges. In typical implementations an incoming data edge is detected by sensing whether the incoming waveform crosses a data threshold level. However, there is some ambiguity in detecting the incoming data edge because PAM-4 modulation has 3 thresholds. If the waveform crosses multiple threshold levels, the level crossings will occur at different time instants due to the finite rise/fall time of the incoming waveform. In this work, we first analyze qualitatively and quantitatively CDR systems that use one threshold for phase adjustment. Here, eliminating the 2-level transitions decreases the amount of jitter injected by the phase detector. However, the available transitions for phase adjustment are also reduced, which lowers the CDR's robustness. Secondly, for CDR systems using three thresholds, a combination of two techniques: majority voting and elimination of 2-level transitions is investigated. We prove that in this case, the elimination of 2-level transitions is not needed and even gives a worse performance when implemented

A high speed serializer/deserializer design

A Serializer/Deserializer (SerDes) is a circuit that converts parallel data into a serial stream and vice versa. It helps solve clock/data skew problems, simplifies data transmission, lowers the power consumption and reduces the chip cost. The goal of this project was to solve the challenges in high speed SerDes design, which included the low jitter design, wide bandwidth design and low power design. A quarter-rate multiplexer/demultiplexer (MUX/DEMUX) was implemented. This quarter-rate structure decreases the required clock frequency from one half to one quarter of the data rate. It is shown that this significantly relaxes the design of the VCO at high speed and achieves lower power consumption. A novel multi-phase LC-ring oscillator was developed to supply a low noise clock to the SerDes. This proposed VCO combined an LC-tank with a ring structure to achieve both wide tuning range (11%) and low phase noise (-110dBc/Hz at 1MHz offset). With this structure, a data rate of 36 Gb/s was realized with a measured peak-to-peak jitter of 10ps using 0.18microm SiGe BiCMOS technology. The power consumption is 3.6W with 3.4V power supply voltage. At a 60 Gb/s data rate the simulated peak-to-peak jitter was 4.8ps using 65nm CMOS technology. The power consumption is 92mW with 2V power supply voltage. A time-to-digital (TDC) calibration circuit was designed to compensate for the phase mismatches among the multiple phases of the PLL clock using a three dimensional fully depleted silicon on insulator (3D FDSOI) CMOS process. The 3D process separated the analog PLL portion from the digital calibration portion into different tiers. This eliminated the noise coupling through the common substrate in the 2D process. Mismatches caused by the vertical tier-to-tier interconnections and the temperature influence in the 3D process were attenuated by the proposed calibration circuit. The design strategy and circuits developed from this dissertation provide significant benefit to both wired and wireless applications