Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series

This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized

Logic Foundry: A Rapid Prototyping Tool for FPGA-based DSP Systems

No abstact submitted. (Also UMIACS-TR-2002-29

Microprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systems

Modern trends in technology require efficient control and processing platforms based on connected software-hardware subsystems. Due to their complexity and size, algorithms implemented on these platforms are difficult to test and verify. When these types of solution are being designed, it is necessary to provide information of the internal values of registers and memories of both the software and hardware during the execution of the complete system. The final architecture of the targeted design and its debugging capabilities strongly depends on how the hybrid system is connected and clocked. This article discusses different architectural strategies that have been adopted for a hybrid hardware-software platform, built ready for debugging, and that uses components that can be easily found with a few special features. All the solutions have been implemented and evaluated using the UNSHADES-2 framework

Constructivist Multi-Access Lab Approach in Teaching FPGA Systems Design with LabVIEW

Embedded systems play vital role in modern applications [1]. They can be found in autos, washing machines, electrical appliances and even in toys. FPGAs are the most recent computing technology that is used in embedded systems. There is an increasing demand on FPGA based embedded systems, in particular, for applications that require rapid time responses. Engineering education curricula needs to respond to the increasing industrial demand of using FPGAs by introducing new syllabus for teaching and learning this subject. This paper describes the development of new course material for teaching FPGA-based embedded systems design by using ‘G’ Programming Language of LabVIEW. A general overview of FPGA role in engineering education is provided. A survey of available Hardware Programming Languages for FPGAs is presented. A survey about LabVIEW utilization in engineering education is investigated; this is followed by a motivation section of why to use LabVIEW graphical programming in teaching and its capabilities. Then, a section of choosing a suitable kit for the course is laid down. Later, constructivist closed-loop model the FPGA course has been proposed in accordance with [2- 4; 80,86,89,92]. The paper is proposing a pedagogical framework for FPGA teaching; pedagogical evaluation will be conducted in future studies. The complete study has been done at the Faculty of Electrical and Electronic Engineering, Aleppo University

Analysis of runtime re-configuration systems

In recent years Programmable Logic Devices (PLD) and in particular Field Programmable Gate Arrays (FPGAs) have seen a tremendous increase in sales and applications in the area of embedded systems. The main advantage of FPGAs is the flexibility that they offer a designer in reconfiguring the hardware. The flexibility achieved through re-configuration of FPGAs usually incurs an overhead of extra execution time, data memory and also power dissipation; FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. Only recently have RTR enabling design tools that bypass the traditional synthesis and bitstream generation process for FPGAs become available, JBits is one of them. With run-time reconfiguration of FPGAs, we can perform partial reconfiguration, which allows reconfiguration of a part of an FPGA while the other part is executing some functional computation. The partial reconfiguration of a function can be performed earlier than the time when the function is really needed. Such configuration pre-fetch can hide the reconfiguration overhead more effectively; This thesis will implement a reconfigurable system and study the effect of runtime reconfiguration using VERILOG and a new Java based tool JBITS. This work will provide pointers to high level synthesis tools targeting runtime re-configuration

Control visual embebido en dispositivo FPGA

El objetivo principal del siguiente proyecto es el diseño e implementación de un controlador visual basado en imagen clásico, embebido en un dispositivo reconfigurable FPGA. Se partirá de un sistema programado sobre la FPGA capaz de procesar una imagen capturada por la cámara. A partir de ésta imagen se obtiene la posición en imagen de los puntos característicos que se emplean para obtener el error del control visual. La principal aportación de este proyecto será la paralelización del algoritmo de control visual para poder programarlo en la FPGA, de forma que se puedan realizar tareas de control visual embebido

Design of Reconfigurable Crossbar Switch for BiNoC Router

this paper presents implementation of 10x10 reconfigurable crossbar switch (RCS) architecture for Dynamic Self-Reconfigurable BiNoC Architecture for Network On Chip. Its main purpose is to increase the performance, flexibility. This paper presents a VHDL based cycle accurate register transfer level model for evaluating the, Power and Area of reconfigurable cross bar switch in BiNoC architectures. We implemented a parameterized register transfer level design of reconfigurable crossbar switch (RCS) architecture. The design is parameterized on (i) size of packets, (ii) length and width of physical links, (iii) number, and depth of arbiters, and (iv) switching technique. The paper discusses in detail the architecture and characterization of the various reconfigurable crossbar switch (RCS) architecture components. The characterized values were integrated into the VHDL based RTL design to build the cycle accurate performance model. In this paper we show the result of simple 10x10 crossbar switch .The results include VHDL simulation of RCS on Xilinx ISE 13.1 software tool