High level behavioural modelling of boundary scan architecture.

This project involves the development of a software tool which enables the integration of the IEEE 1149.1/JTAG Boundary Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the two major elements: i) A parsing and insertion algorithm developed and implemented in 'C'; ii) A high level model of the Boundary Scan Test Architecture implemented in 'VHDL'. The parsing and insertion algorithm is developed to deal with identifying the design Input/Output (I/O) terminals, their types and the order they appear in the ASIC design. It then attaches suitable Boundary Scan Cells to each I/O, except power and ground and inserts the high level models of the full Boundary Scan Architecture into the ASIC without altering the design core structure

Project OASIS: The Design of a Signal Detector for the Search for Extraterrestrial Intelligence

An 8 million channel spectrum analyzer (MCSA) was designed the meet to meet the needs of a SETI program. The MCSA puts out a very large data base at very high rates. The development of a device which follows the MCSA, is presented

Reliability Analysis of On-Demand High-Speed Machining

Current trends in high-speed machining aim to increase manufacturing efficiency by maximizing material removal rates and minimizing part cycle times. This project explores three related technologies and presents a system design for rapid production of custom machined parts. First a reliability analysis in high-speed machining of thin wall features is put forth with experimental results. Second an implementation of on-demand manufacturing is presented with emphasis on flexibility and automation. Finally innovative manufacturing cell design is used to drive costs down by optimizing material and information flow. The resulting high-speed on-demand machining cell design employs effective techniques to reduce production time, meet changing customer needs, and drive down costs

Nanometer-precision electron-beam lithography with applications in integrated optics

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (p. 179-185).Scanning electron-beam lithography (SEBL) provides sub-10-nm resolution and arbitrary-pattern generation; however, SEBL's pattern-placement accuracy remains inadequate for future integrated-circuits and integrated-optical devices. Environmental disturbances, system imperfections, charging, and a variety of other factors contribute to pattern-placement inaccuracy. To overcome these limitations, spatial-phase locked electron-beam lithography (SPLEBL) monitors the beam location with respect to a reference grid on the substrate. Phase detection of the periodic grid signal provides feedback control of the beam position to within a fraction of the period. Using this technique we exposed patterns globally locked to a fiducial grid and reduced local field-stitching errors to a < 1.3 nm. Spatial-phase locking is particularly important for integrated-optical devices that require pattern-placement accuracy within a fraction of the wavelength of light. As an example, Bragg-grating based optical filters were fabricated in silicon-on-insulator waveguides using SPLEBL. The filters were designed to reflect a narrow-range of wavelengths within the communications band near 1550-nm. We patterned the devices in a single lithography step by placing the gratings in the waveguide sidewalls. This design allows apodization of the filter response by lithographically varying the grating depth. Measured transmission spectra show greatly reduced sidelobe levels for apodized devices compared to devices with uniform gratings.by Jeffrey Todd Hastings.Ph.D

Digital Image Access & Retrieval

The 33th Annual Clinic on Library Applications of Data Processing, held at the University of Illinois at Urbana-Champaign in March of 1996, addressed the theme of "Digital Image Access & Retrieval." The papers from this conference cover a wide range of topics concerning digital imaging technology for visual resource collections. Papers covered three general areas: (1) systems, planning, and implementation; (2) automatic and semi-automatic indexing; and (3) preservation with the bulk of the conference focusing on indexing and retrieval.published or submitted for publicatio

Development of PCI Embedded Card Useful for Microcontroller Trainer

Not availabl

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers