Modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors

We introduce and experimentally validate a new macro-level model of the CPU temperature/power relationship within nanometer-scale application processors or system-on-chips. By adopting a holistic view, this model is able to take into account many of the physical effects that occur within such systems. Together with two algorithms described in the paper, our results can be used, for instance by engineers designing power or thermal management units, to cancel the temperature-induced bias on power measurements. This will help them gather temperature-neutral power data while running multiple instance of their benchmarks. Also power requirements and system failure rates can be decreased by controlling the CPU's thermal behavior. Even though it is usually assumed that the temperature/power relationship is exponentially related, there is however a lack of publicly available physical temperature/power measurements to back up this assumption, something our paper corrects. Via measurements on two pertinent platforms sporting nanometer-scale application processors, we show that the power/temperature relationship is indeed very likely exponential over a 20{\deg}C to 85{\deg}C temperature range. Our data suggest that, for application processors operating between 20{\deg}C and 50{\deg}C, a quadratic model is still accurate and a linear approximation is acceptable.Comment: Submitted to SAMOS 2014; International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV

150°C amorphous silicon thin-film transistor technology for polyimide substrates

We have developed a 150°C technology for amorphous silicon thin-film transistors (a-Si:H TFTs) on polyimide substrates deposited by plasma enhanced chemical vapor deposition. The silicon nitride gate dielectric and the a-Si:H channel material were tailored to provide the least leakage current and midgap defect density, respectively. In addition, we conducted experiments on the TFT structure and fabrication with the aim of obtaining high electron mobility. TFTs with back-channel etch and channel-passivated structures were fabricated on glass or 51 μm thick polyimide foil. The a-Si:H TFTs have an on/off current ratio of ∼10 7 and an electron mobility of ∼0.7 cm 2/V s

Effects of Bulk and Surface Conductivity on the Performance of CdZnTe Pixel Detectors

We studied the effects of bulk and surface conductivity on the performance of high-resistivity CdZnTe (CZT) pixel detectors with Pt contacts. We emphasize the difference in mechanisms of the bulk and surface conductivity as indicated by their different temperature behaviors. In addition, the existence of a thin (10-100 A) oxide layer on the surface of CZT, formed during the fabrication process, affects both bulk and surface leakage currents. We demonstrate that the measured I-V dependencies of bulk current can be explained by considering the CZT detector as a metal-semiconductor-metal system with two back-to-back Schottky-barrier contacts. The high surface leakage current is apparently due to the presence of a low-resistivity surface layer that has characteristics which differ considerably from those of the bulk material. This surface layer has a profound effect on the charge collection efficiency in detectors with multi-contact geometry; some fraction of the electric field lines originated on the cathode intersects the surface areas between the pixel contacts where the charge produced by an ionizing particle gets trapped. To overcome this effect we place a grid of thin electrodes between the pixel contacts; when the grid is negatively biased, the strong electric field in the gaps between the pixels forces the electrons landing on the surface to move toward the contacts, preventing the charge loss. We have investigated these effects by using CZT pixel detectors indium bump bonded to a custom-built VLSI readout chip