Reliability analysis of foil substrate based integration of silicon chips

Flexible electronics has attracted significant attention in the recent past due to the booming wearables market in addition to the ever-increasing interest for faster, thinner and foldable mobile phones. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 μm are flexible and therefore they can be integrated on or in polymer foils to create flexible hybrid electronic (FHE) components that could be used to replace rigid standard surface mount device (SMD) components. The fabricated FHE components referred as chip foil packages (CFPs) in this work are ideal candidates for FHE system integration owing to their ability to deliver high performance at low power consumption while being mechanically flexible. However, very limited information is available in the literature regarding the reliability of CFPs under static and dynamic bending. The lack of such vital information is a major obstacle impeding their commercialization. With the aim of addressing this issue, this thesis investigates the static and dynamic bending reliability of CFPs. In this scope, the static bending reliability of CFPs has been investigated in this thesis using flexural bending tests by measuring their fracture strength. Then, Finite Element Method (FEM) simulations have been implemented to calculate the fracture stress of ultra-thin flexible silicon chips where analytical formulas may not be applied. After calculating the fracture stress from FEM simulations, the enhancement in robustness of ultra-thin chips (UTCs) against external load has also been proved and quantified with further experimental investigations. Besides, FEM simulations have also been used to analyse the effect of Young’s Modulus of embedding materials on the robustness of the embedded UTCs. Furthermore, embedding the UTCs in polymer layers has also been experimentally proven to be an effective solution to reduce the influence of thinning and dicing induced damages on the robustness of the embedded UTCs. Traditional interconnection techniques such as wire bonding may not be implemented to interconnect ultra-thin silicon ICs owing to the high mechanical forces involved in the processes that would crack the chips. Therefore, two novel interconnection methods namely (i) flip-chip bonding with Anisotropic Conductive Adhesive (ACA) and (ii) face-up direct metal interconnection have been implemented in this thesis to interconnect ultra-thin silicon ICs to the corresponding interposer patterns on foil substrates. The CFP samples thus fabricated were then used for the dynamic bending reliability investigations. A custom-built test equipment was developed to facilitate the dynamic bending reliability investigations of CFPs. Experimental investigations revealed that the failure of CFPs under dynamic bending was caused mainly by the cracking of the redistribution layer (RDL) interconnecting the chip and the foil. Furthermore, it has also been shown that the CFPs are more vulnerable to repeated compressive bending than to repeated tensile bending. Then, the influence of dimensional factors such as the thickness of the chip as well as the RDL on the dynamic bending reliability of CFPs have also been studied. Upon identifying the plausible cause behind the cracking of the RDL leading to the failure of the CFPs, two methods to improve the dynamic bending reliability of the RDL have been suggested and demonstrated with experimental investigations. The experimental investigations presented in this thesis adds some essential information to the state-of-the-art concerning the static and the dynamic bending reliability of UTCs integrated in polymer foils that are not yet available in the literature and aids to establish in-depth knowledge of mechanical reliability of the components required for manufacturing future FHE systems. The strategies devised to enhance the robustness of UTCs and CFPs could serve as guidelines for fabricating reliable FHE components and systems

Die separation strength for deep reactive ion etched wafers.

In the electronic and microfabrication industry, die separation is one of the most critical steps in producing an undamaged, stand-alone micro-scale device. For silicon based devices, it is the predominant step governing resistance to die failure by mechanical fracture. Traditional separation methods include the use of dicing saws and/or backside grinding to dice-by-thinning. Excessive forces, vibrations, and surface contact involved with these methods can cause undesirable side-wall chipping and microcracking, which often translates to inoperable devices. Deep Reactive Ion Etching (DRIE) offers an alternative technique for die separation with less mechanical force. The DRIE process may be used to either introduce notches in one uniform step that allow for die separation via fracture in three-point bending, or to directly separate the dies by etching completely through the substrate. This work presents an analysis of the stress concentrations due to DRIE etched notches and the bending stress required to achieve die separation. The defect rate and die strength associated with DRIE-based die separated is compared with traditional saw methods for a variety of notch depths. Results indicate that the DRIE-based separation technique offers modest advantages over the traditional methods, but can also greatly reduce strength if the protective mask is over etched. It will also show that shallow trenches formed by a mechanical dicing saw resulted in stronger die than deeper trenches

Al-Al thermocompression bonding for wafer-level MEMS sealing

Al–Al thermocompression bonding has been studied using test structures relevant for wafer level sealing of MEMS devices. Si wafers with protruding frame structures were bonded to planar Si wafers, both covered with a sputtered Al film of 1 μm thickness. The varied bonding process variables were the bonding temperature (400, 450 and 550 °C) and the bonding force (18, 36 and 60 kN). Frame widths 100 μm, 200 μm, with rounded or sharp frame corners were used. After bonding, laminates were diced into single chips and pull tested. The effect of process and design parameters was studied systematically with respect to dicing yield, bond strength and resulting fractured surfaces. The test structures showed an average strength of 20–50 MPa for bonding at or above 450 °C for all three bonding forces or bonding at 400 °C with 60 kN bond force. The current study indicates that strong AlAl thermocompression bonds can be achieved either at or above 450 °C bonding temperature for low (18 kN) and medium (36 kN) bond force or by high bond force (60 kN) at 400 °C. The results show that an increased bond force is required to compensate for a reduced bonding temperature for AlAl thermocompression bonding in the studied temperature regimeacceptedVersio

Study and characetrization of plastic encapsulated packages for MEMS

Technological advancement has thrust MEMS design and fabrication into the forefront of modern technologies. It has become sufficiently self-sustained to allow mass production. The limiting factor which is stalling commercialization of MEMS is the packaging and device reliability. The challenging issues with MEMS packaging are application specific. The function of the package is to give the MEMS device mechanical support, protection from the environment, and electrical connection to other devices in the system. The current state of the art in MEMS packaging transcends the various packaging techniques available in the integrated circuit (IC) industry. At present the packaging of MEMS includes hermetic ceramic packaging and metal packaging with hermetic seals. For example the ADXL202 accelerometer from the Analog Devices. Study of the packaging methods and costs show that both of these methods of packaging are expensive and not needed for majority of MEMS applications. Due to this the cost of current MEMS packaging is relatively high, as much as 90% of the finished product. Reducing the cost is therefore of the prime concern. This Thesis explores the possibility of an inexpensive plastic package for MEMS sensors like accelerometers, optical MEMS, blood pressure sensors etc. Due to their cost effective techniques, plastic packaging already dominates the IC industry. They cost less, weigh less, and their size is small. However, porous nature of molding materials allows penetration of moisture into the package. The Thesis includes an extensive study of the plastic packaging and characterization of three different plastic package samples. Polymeric materials warp upon absorbing moisture, generating hygroscopic stresses. Hygroscopic stresses in the package add to the thermal stress due to high reflow temperature. Despite this, hygroscopic characteristics of the plastic package have been largely ignored. To facilitate understanding of the moisture absorption, an analytical model is presented in this Thesis. Also, an empirical model presents, in this Thesis, the parameters affecting moisture ingress. This information is important to determine the moisture content at a specific time, which would help in assessing reliability of the package. Moisture absorption is modeled using the single phase absorption theory, which assumes that moisture diffusion occurs freely without any bonding with the resin. This theory is based on the Fick\u27s Law of diffusion, which considers that the driving force of diffusion is the water concentration gradient. A finite difference simulation of one-dimensional moisture diffusion using the Crank-Nicolson implicit formula is presented. Moisture retention causes swelling of compounds which, in turn, leads to warpage. The warpage induces hygroscopic stresses. These stresses can further limit the performance of the MEMS sensors. This Thesis also presents a non invasive methodology to characterize a plastic package. The warpage deformations of the package are measured using Optoelectronic holography (OEH) methodology. The OEH methodology is noninvasive, remote, and provides results in full-field-of-view. Using the quantitative results of OEH measurements of deformations of a plastic package, pressure build up can be calculated and employed to assess the reliability of the package

Gallium-based Solid Liquid Interdiffusion Bonding of Semiconductor Substrates near room temperature

Within this work, bonding technologies based upon the alloying of gallium with other metals to assemble semiconductor substrates for the possible application of encapsulation and 3D-integration of micro systems and devices have been researched. Motivated by the important demand to achieve low temperature processes, methods with bonding temperatures below 200°C were investigated. Necessary technologies like the deposition of gallium as thin film and subsequent micro structuring have been developed. The alloying between gallium and gold as well as gallium and copper was analysed in detail. A good correlation between the elemental composition of the interface and its mechanical and electrical parameters was established, particularly regarding its thermal dependence. It emerged that in case of combination Au/Ga Kirkendall void are extensively formed whereby serious problems with mechanical strength as well as hermeticity emerged. In case of Cu/Ga, this problem is existent to a much lesser degree; it was possible to create hermetic tight bonds. For the necessary pre-treatment of copper, several methods could be successfully demonstrated. In summary, the development of bonding technologies based upon metallic interfaces that exhibit electric conductance, high strength and hermetic seal could be demonstrated.In dieser Arbeit werden Bondverfahren zum Fügen von Halbleitersubstraten für mögliche Anwendungen für die Verkapselung und 3D-Integration von Bauelementen der Mikrosystemtechnik erforscht, die auf der Legierungsbildung von Gallium mit anderen Metallen beruhen. Motiviert von der zentralen Anforderung an niedrige Prozesstemperaturen wurden Methoden mit Fügetemperaturen deutlich unter 200°C untersucht. Dafür nötige Technologien zum Abscheiden von Gallium als Dünnschicht und das anschließende Mikrostrukturieren wurden entwickelt. Die Legierungsbildung zwischen Gallium und Gold sowie zwischen Gallium und Kupfer wurde im experimentell im Detail analysiert. Dabei konnte eine gute Korrelation zwischen der stofflichen Zusammensetzung und den mechanischen bzw. elektrischen Parametern der Zwischenschicht, auch und insbesondere hinsichtlich ihrer Temperaturabhängigkeit gefunden werden. Es stellte sich heraus, dass im Falle der Kombination Au/Ga Kirkendall Hohlräume in einer Menge entstehen, die zu erheblichen Problemen bezüglich mechanischer Festigkeit und Dichtheit der Fügeverbindung führen. Bei der Materialkombination Cu/Ga hingegen trat dieses Problem nur begrenzt auf; es war möglich hermetisch dichte Verbindungen herzustellen. Für die bei Kupfer nötige Vorbehandlung wurden mehrere Methoden erfolgreich getestet. Insgesamt konnte die Entwicklung von Fügetechnologien gezeigt werden, die metallische Zwischenschichten verwenden, elektrisch leitfähig sind, sehr gute Festigkeiten aufweisen und hermetisch dicht sind

Laser-based packaging of micro-devices

In this PhD thesis the development of laser-based processes for packaging applications in microsystems technologies is investigated. Packaging is one of the major challenges in the fabrication of micro-electro-mechanical systems (MEMS) and other micro-devices. A range of bonding processes have become established in industry, however, in many or even most cases heating of the entire package to the bonding temperature is required to effect efficient and reliable bonding. The high process temperatures of up to 1100°C involved severely limit the application areas of these techniques for packaging of temperature sensitive materials. As an alternative production method, two localised heating processes using a laser were developed where also the heat is restricted to the joining area only by active cooling. Silicon to glass joining with a Benzocyclobutene adhesive layer was demonstrated which is a typical MEMS application. In this laser-based process the temperature in the centre of the device was kept at least 120°C lower than in the bonding area. For chip-level packaging shear forces as high as 290 N were achieved which is comparable and some cases even higher than results obtained using conventional bonding techniques. Furthermore, a considerable reduction of the bonding time from typically 20 minutes down to 8 s was achieved. A further development of this process to wafer-level packaging was demonstrated. For a simplified pattern of 5 samples the same quality of the seal could be achieved as for chip-level packaging. Packaging of a more densely packed pattern of 9 was also investigated. Successful sealing of all nine samples on the same wafer was demonstrated proving the feasibility of wafer-level packaging using this localised heating bonding process. The development of full hermetic glass frit packaging processes of Leadless Chip Carrier (LCC) devices in both air and vacuum is presented. In these laser-based processes the temperature in the centre of the device was kept at least 230°C below the temperature in the joining region (375°C to 440°C). Testing according to MIL-STD-883G showed that hermetic seals were achieved in high yield processes (>90%) and the packages did withstand shear forces in excess of 1 kN. Residual gas analysis has shown that a moderate vacuum of around 5 mbar was achieved inside the vacuum packaged LCC devices. A localised heating glass frit packaging process was developed without any negative effect of the thermal management on the quality of the seal

MEMS suljenta kuparin lämpöpuristusliitännällä

Copper thermocompression is a promising wafer-level packaging technique, as it allows the bonding of electric contacts simultaneously to hermetic encapsulation. In thermocompression bonding the bond is formed by diffusion of atoms from one bond interface to another. The diffusion is inhibited by barrier forming surface oxide, high surface roughness and low temperature. Aim of this study was to establish a wafer-level packaging process for MEMS (Mi-croElectroMechanical System) mirror and MEMS gyroscope. The cap wafer of the MEMS mirror has an antireflective coating that limits the thermal budget of the bonding process to 250°C. This temperature is below the eutectic temperature of most common eutectic bonding materials, such as Au-Sn (278°C), Au-Ge (361°C) and Au-Si (370°C). Thus a thermocompression bonding method needed to be developed. Copper was used as a bonding material due to its low cost, high self-diffusivity and resistance to oxidation in ambient air. The bond structures were fabricated using three different methods and the bonding was further enhanced by annealing. The bonded structures were characterized with scanning acoustic microscopy, scanning electron microscope and the bond strength was determined by shear testing. Exposing the bond structures to etchant during Cu seed layer removal was found to drastically increase the surface roughness of bond structures. This increase proved detrimental to bond strength and dicing yield and thus covering the bond surface during wet etching is recommended. The native oxidation on copper surfaces was completely removed with combination of ex situ acetic acid wet etch and in situ forming gas anneal. Successful thermocompression bonding process using sputtered copper films was established at a low temperature of 200°C, well below the thermal limitation set by the antireflective coating. The established wafer bonding process had high yield of 97% after dicing. The bond strength was evaluated by maximum shear strength and recorded at 75 MPa, which is well above the MIL-STD-883E standard (METHOD 2019.5) rejection limit of 6.08 MPa.Kuparin lämpöpuristusliitäntä on lupaava kiekkotason pakkausmenetelmä, sillä se mahdollistaa sekä sähköisten liitäntöjen, että hermeettisen suljennan toteuttamisen samanaikaisesti. Lämpöpuristusliitännässä sidos muodostuu atomien diffuusiosta liitospinnalta toiselle. Diffuusiota rajoittavat estokerroksen muodostava pinta oksidi, korkea pinnan karheus ja matala lämpötila. Diplomityön tavoitteena oli luoda kiekkotason pakkausmenetelmä mikroelektromekaaniselle (MEMS, MicroElectroMechanical System) peilille ja MEMS gyroskoopille. Peilin lasisen kansikiekon pinnalla oleva antiheijastava kalvo rajoitti liitännässä käytettävän lämpötilan korkeintaan 250°C:een, mikä on alempi lämpötila kuin useimpien kiekkoliitännässä käytettyjen materiaaliparien eutektinen piste. Esimerkkinä mainittakoon mm. Au-Sn (278°C), Au-Ge (361°C) ja Au-Si (370°C). Kuparin alhainen hinta, korkea ominaisdiffuusio ja hidas hapettuminen ilmakehässä puoltavat sen valintaa liitäntämateriaaliksi. Liitäntärakenteet valmistettiin kolmella menetelmällä ja liitännän vahvuutta parannettiin lämpökäsittelyllä. Liitetyt rakenteet karakterisoitiin pyyhkäisy elektronimikroskoopin, akustisen mikroskoopin ja liitoslujuus-mittauksen avulla. Liitospintojen altistamisen hapolle havaittiin lisäävän pinnankarkeutta ja olevan siten haitallista liitokselle ja laskevan saantoa. Liitospintojen suojaaminen siemenkerroksen syövytyksen aikana on suotavaa. Pintaoksidi pystytään poistamaan täysin suorittamalla oksidin märkäetsaus jääetikalla sekä lämpökäsittely N2/H2 atmosfäärissä. Sputteroidut kuparikalvot pystyttiin liittämään onnistuneesti yhteen 200°C lämpötilassa, mikä on alle anti-heijastavan pinnan asettaman lämpötilarajan. Tällä liitäntä menetelmällä saavutettiin kiekkoliitoksella yhteen liitettyjen sirujen sahauksessa korkea 97% saanto. Liitoslujuus määritettiin maksimi-leikkausvoiman avulla ja sen suuruudeksi mitattiin 75 MPa. Lujuus oli yli kymmenkertainen MIL-STD-883E standardin (METHOD 2019.5) asettamaan hylkäysrajaan 6.08 MPa nähden

Low-power silicon planar micro-calorimeter employing nanostructured catalyst

This thesis describes the development of silicon planar micro-calorimetric gas sensors employing a nanostructured palladium (Pd) catalyst. Present commercial, bead-type calorimetric sensors have been manufactured for nearly forty years and are used in many applications, such as mining, water treatment and emergency services, with an estimated European market value of €221M by 2004. However, recent advances in both silicon micro-machining and nano materials have created the technologies necessary to transform the present labour-intensive fabrication process in to a new low-cost batch production. In addition, a reduction in power consumption, improved sensitivity and increased poisoning resistance of the sensor can also be achieved. Here, two generations of micro-calorimeter have been designed and fabricated comprising a silicon membrane structured micro-hotplate that can reach up to a temperature of 870'C without failure and an ultra-high surface area nanoporous Pd catalyst (about 20 m2/g), typically 25 run thick, deposited electrochemically on top of a gold electrode above the micro-heater. The exothermic reaction caused by the target gas (e.g. methane) interacting with the Pd catalyst results in an increase in the temperature and so resistance of the micro-heater. A Wheatstone bridge interface circuit is normally used to detect and measure the fractional resistance change. Full 3-D thermo-mechanical simulations have been performed employing experimental data in order to establish a simulation database for future developments. The differences between simulated and experimental results were found to be as low as 4.6%. The response of the sensors has been characterised in both continuous powering mode and pulse modulation powering mode. Device power consumption is only 50mW at 500'C in continuous mode, which is up to 100mW lower than that for commercial sensors. Typical response times of 2ms have been measured and so further power saving can be achieved when the sensors are operated in a pulse mode, e.g. 50% duty-cycle at 10Hz. Hence, an overall power saving of 75% could be achieved compared to commercial product. Infrared thermography revealed that a centre hot spot, commonly found with meander style micro-heaters, has been eliminated by the new drive-wheel micro-heater design. The sensitivity of the sensors has also been improved, up to a factor of 4 at 500'C ((60 mV/mm2)/%CH4), by the nanoporous catalyst and by heating it more isothermally. Furthermore, improvements have also been found on the poisoning resistance. Therefore, the potential commercialisation of the micro-calorimeter is very promising

Wafer level chip scale packaging using wafer bonder

An in-house processing capability is developed in this research for silicon-glass bonding for microfabrication and wafer level chip scale packaging (WLCSP) using a wafer bonder. New masking technology for wet etching of glass to a depth of more than 430 µm is reported in this research work along with development of an anodic bonding process that permits electrical feedthroughs for connections to outside world. Three novel masks were developed in this work for deep wet etching of glass. They were multilayers of metals Mo/Cr/Au (mask 1) and Cr/Au/electroplated Ni (mask 2) both in combination with 20 µm thick AZ® P4620 photoresist and anodically bonded silicon (mask 3). Etch depths greater than 600 µm in glass has been achieved using anodically bonded silicon mask 3 above. It may be currently the only method available to achieve etch depths of 1 mm in glass. Earlier barrier of 300 µm etch depth in glass using multilayer metal mask has effectively been broken in this work with an etch depth of 430 µm achieved using electroplated Ni mask 2) above. A high value of 0.88 for the aspect ratio, defined as the ratio of the vertical etch depth to the lateral etch distance, was achieved using mask 1) above. The problem of etched surface roughness observed in glass with undiluted HF etching has been alleviated by use of a combination of 50:5:1 by volume HF:HCl:HNO3. Etch depths of 355 µm has been achieved in silicon using 45 % KOH solution at 50 °C with 1 µm thick oxide mask. The above etch parameters also resulted in smooth etched mirror like surfaces, sharp edges in etched pits and deep trenches in silicon. The decontaminated etched glass and silicon substrates were aligned in-situ and bonded using an AML 402 wafer bonder. The corner areas of the glass wafer were diced to expose the metal lines permitting electrical communication from the anodically bonded packaged chip to the outside world. The concept of WLCSP using anodic bonding has been developed and demonstrated in this research