GaN-based HEMTs for Cryogenic Low-Noise Applications

Radio-astronomy deals with signals and radiations of extremely weak intensity. Also, it requires robust and rugged technologies able to sustain and prevent the Radio Frequency Interferences (RFI). Complying with the required high sensitivity, Low Noise Amplifiers (LNAs) operating at cryogenic temperatures are key elements in radio astronomy instrumentation. Thus far, advanced semiconductor technologies but with limited power-handling capabilities have been traditionally employed as LNAs. Over the past decades, Gallium Nitride (GaN)-based high electron mobility transistors (HEMTs) were demonstrated at room temperature to offer a combination of both excellent low-noise operation and a superior high-power handling performance compared to other materials. In addition, a number of studies indicated a promising potential for the GaN technology to operate at cryogenic temperatures. However, the cryogenic noise performance of the GaN-HEMTs remained unexplored so far.This thesis investigates the potential of GaN–based HEMTs for low-noise operation at these cryogenic temperatures. Established characterization and modeling approaches were employed for this purpose. As a main result, this work reveals a first estimation of the noise performance of GaN-HEMTs at cryogenic temperatures of ~10 K which compares to other more advanced technologies in this field. This was achieved through the extraction of a model, based on experimental noise measurements, describing the microwave noise behavior at cryogenic temperatures at the device level. The model predicts the noise contribution of GaN-HEMTs at cryogenic temperatures with respect to the frequency of operation, the dissipated power, and the total periphery of the device. Hence, it constitutes the basis for the design of future GaN-based LNAs which fulfill the different requirements set by the demanding cryogenic applications.The extracted cryogenic noise model was used to identify and analyze the role of the different physical parameters of the device, over which a technological control might be possible in the future in order to improve the assessed noise performance of the cryogenic GaN-HEMTs. From that perspective, GaN-HEMTs featuring superconducting Niobium (Nb)-gates were demonstrated for the first time. The successful integration of superconducting Nb-gates into AlGaN/GaN HEMTs was demonstrated on different samples, showing a suppression of the gate resistance independently of the width and length of the gate below a critical temperature \u1d447\u1d450 < 9.2 K. The superconductivity of the gate leads to the cancellation of the associated noise contribution. Comparing the noise performance of the resulting devices to that of the conventional Gold (Au)-gated GaN-HEMTs, it was concluded that further management of the device’s self-heating is required to enable the full potential of the Nb-gate by maintaining its superconductivity while operating at optimum-noise bias conditions

ProtoEXIST: Advanced Prototype CZT Coded Aperture Telescopes for EXIST

{\it ProtoEXIST1} is a pathfinder for the {\it EXIST-HET}, a coded aperture hard X-ray telescope with a 4.5 m$^2$ CZT detector plane a 90$\times$70 degree field of view to be flown as the primary instrument on the {\it EXIST} mission and is intended to monitor the full sky every 3 h in an effort to locate GRBs and other high energy transients. {\it ProtoEXIST1} consists of a 256 cm$^2$ tiled CZT detector plane containing 4096 pixels composed of an 8$\times$8 array of individual 1.95 cm $\times$ 1.95 cm $\times$ 0.5 cm CZT detector modules each with a 8 $\times$ 8 pixilated anode configured as a coded aperture telescope with a fully coded $10^\circ\times10^\circ$ field of view employing passive side shielding and an active CsI anti-coincidence rear shield, recently completed its maiden flight out of Ft. Sumner, NM on the 9th of October 2009. During the duration of its 6 hour flight on-board calibration of the detector plane was carried out utilizing a single tagged 198.8 nCi Am-241 source along with the simultaneous measurement of the background spectrum and an observation of Cygnus X-1. Here we recount the events of the flight and report on the detector performance in a near space environment. We also briefly discuss {\it ProtoEXIST2}: the next stage of detector development which employs the {\it NuSTAR} ASIC enabling finer (32$\times$32) anode pixilation. When completed {\it ProtoEXIST2} will consist of a 256 cm$^2$ tiled array and be flown simultaneously with the ProtoEXIST1 telescope

Gate-to-channel parasitic capacitance minimization and source-drain leakage evaluation in germanium PMOS

This work studies the behavior of both gate-to-channel capacitance (CGC) and source-channel-drain/well leakage in metal-gate/high-κ/Ge PMOS technology (W = 10 μm and L = 10; 5; 1 μm) under development at IMEC. The hole drift-mobility of germanium is ~4X that of silicon, leading researchers to evaluate germanium as a possible channel material replacement for PMOS expected at the 32 nm technology node. In particular this study focuses on—but is not restricted to—(1) the presence of a parasitic gate-to-channel capacitance (CGC), the large non-ideal trap assisted conductance which contributes to it, and its function versus Ge-PMOS architecture and gate length; (2) the existence of C-V tool compensation error due to CGC measurement technique resulting in conductance measurement error; (3) the presence of large source-channel-drain/well leakages characterized using a new MOS gated-diode measurement technique; (4) extrinsic capacitance (CEXT), flatband voltage (VFB), and effective oxide thickness (EOT) parameter extraction with discussion on inversion layer quantization. This study found that excessive current leakages from the Ge-PMOS source-anddrain into the channel led to a chuck-dependent parasitic capacitance during CGC measurement. This excessive leakage is identified as a trap-assisted leakage through both AC and DC analysis. The chuck-dependent parasitic capacitance was an unexpected side effect of the PMOS architecture: namely the lack of N-Well isolation. The parasitic capacitance—dependent on both applied bias and frequency—was separated into two main capacitive components: a frequency-dependent source/well and drain/well trapassisted leakage capacitance (CPara_SD) and a frequency-voltage-dependent gate-induced iv junction leakage capacitance (CPara_GIJL). A third parasitic capacitance due to interface trap (IT) contribution (CIT) during channel depletion was also identified. This study also found that the new MOS gated-diode measurement technique designed to separate and evaluate the source, channel, and drain leakage components is superior to typical VGS versus IDS methods when attempting to quantify the CGC measurement. The MOS gated-diode configuration allowed for temperature-dependent analysis and activation energy extraction (EA), thereby providing a means to confirm individual leakage components: diffusion; Shockley-Read-Hall (SRH); trap-assisted leakage (TAL). TAL components include: Poole-Frenkel (PF); phonon-assisted tunneling (PAT); trap-to-band tunneling (TBT). In conclusion, it was found that the source-channel-drain/well leakages and hence parasitic capacitances of PMOS built on relaxed germanium-on-silicon can be minimized by reducing the source/drain area, reducing the source/drain-to-gate contact distance, while increasing both the gate length and measurement frequency. The dominance of SRH and TAL during Ge-PMOS operation disagrees with diffusion dominance predicted by theory and as a result opens the door for future research. Future research includes Ge- PMOS fabrication on substrates free of dislocations—to minimize SRH and TAL current leakage contributions—so as to compare leakage performance

Electrical characterization of thin film passivation layers for p-type silicon solar cells

Le celle solari in Silicio monocristallino costituiscono una delle principali tecnologie fotovoltaiche. Uno degli aspetti più limitanti è il prezzo del Silicio: circa il 70% del costo di una cella completa deriva dal substrato siliceo. Una soluzione è ridurne la quantità utilizzata, diminuendo lo spessore del wafer. Tuttavia, questo porta un forte aumento del tasso di ricombinazione superficiale (specie al rear contact della cella) ed una conseguente diminuzione dell’efficienza. Una soluzione per risolvere o quantomeno limitare quest’effetto è la “passivazione”. Un sottile strato di materiale dielettrico (in questo lavoro Al2O3 e HfO2) è depositato sopra il wafer di Silicio, (i) riducendo la densità di trappole all’interfaccia Silicio/dielettrico e (ii) creando un opportuno campo elettrico in grado di opporsi alla ricombinazione. (i) e (ii) sono noti come passivazione chimica e passivazione per effetto di campo. Questo lavoro cerca di caratterizzare i due meccanismi tramite misure elettriche su substrati passivati di Silicio-

Design and Control of Power Converters for High Power-Quality Interface with Utility and Aviation Grids

Power electronics as a subject integrating power devices, electric and electronic circuits, control, and thermal and mechanic design, requires not only knowledge and engineering insight for each subarea, but also understanding of interface issues when incorporating these different areas into high performance converter design.Addressing these fundamental questions, the dissertation studies design and control issues in three types of power converters applied in low-frequency high-power transmission, medium-frequency converter emulated grid, and high-frequency high-density aviation grid, respectively, with the focus on discovering, understanding, and mitigating interface issues to improve power quality and converter performance, and to reduce the noise emission.For hybrid ac/dc power transmission,• Analyze the interface transformer saturation issue between ac and dc power flow under line unbalances.• Proposed both passive transformer design and active hybrid-line-impedance-conditioner to suppress this issue.For transmission line emulator,• Propose general transmission line emulation schemes with extension capability.• Analyze and actively suppress the effects of sensing/sampling bias and PWM ripple on emulation considering interfaced grid impedance.• Analyze the stability issue caused by interaction of the emulator and its interfaced impedance. A criterion that determines the stability and impedance boundary of the emulator is proposed.For aircraft battery charger,• Investigate architectures for dual-input and dual-output battery charger, and a three-level integrated topology using GaN devices is proposed to achieve high density.• Identify and analyze the mechanisms and impacts of high switching frequency, di/dt, dv/dt on sensing and power quality control; mitigate solutions are proposed.• Model and compensate the distortion due to charging transition of device junction capacitances in three-level converters.• Find the previously overlooked device junction capacitance of the nonactive devices in three-level converters, and analyze the impacts on switching loss, device stress, and current distortion. A loss calculation method is proposed using the data from the conventional double pulse tester.• Establish fundamental knowledge on performance degradation of EMI filters. The impacts and mechanisms of both inductive and capacitive coupling on different filter structures are understood. Characterization methodology including measuring, modeling, and prediction of filter insertion loss is proposed. Mitigation solutions are proposed to reduce inter-component coupling and self-parasitics

Electromagnetic Interference and Compatibility

Recent progress in the fields of Electrical and Electronic Engineering has created new application scenarios and new Electromagnetic Compatibility (EMC) challenges, along with novel tools and methodologies to address them. This volume, which collects the contributions published in the “Electromagnetic Interference and Compatibility” Special Issue of MDPI Electronics, provides a vivid picture of current research trends and new developments in the rapidly evolving, broad area of EMC, including contributions on EMC issues in digital communications, power electronics, and analog integrated circuits and sensors, along with signal and power integrity and electromagnetic interference (EMI) suppression properties of materials

Final Report: Theory of Advanced High Efficiency Concentrator Cells

The goal of this project was to begin -developing accurate, and ultimately predictive, device models for III-V concentrator cells. The project consisted of extending a one-dimensional numerical device model previously developed at Purdue to III-V solar cells. We also began verifying the accuracy of the code by comparing computed and measured solar cell characteristics. Gallium arsenide was selected because it is the most mature III-V technology and because GaAs solar cells have demonstrated high conversion efficiency [l,2,3]. The present device model should be useful in optimizing GaAs solar cells and forms a foundation that can be extended to other III-V homo- and heterostructure solar cells. The numerical device model developed in this work solves Poisson’s equation simultaneously with the electron and hole continuity equations without making common assumptions such as low-level injection, piece-wise uniform doping, neglect of space-charge recombination, etc. Materials models for GaAs solar cells (e. g. intrinsic carrier concentration, carrier mobilities, lifetimes, optical absorption and reflection coefficients, etc.) were compiled, evaluated, and in some cases extended. These materials models were then implemented into the numerical device model. The device model was also extended to analyze optical absorption and reflection from bare and anti-reflection (AR) coated cells. To test the GaAs cell model, we compared its predictions to measured results for an N+P cell (the shallow homojunction cell reported by Fan and co-workers) and a P+N cell (fabricated by Borrego and co-workers). In general, good agreement between theory and experiment was obtained for both concentrated and unconcentrated conditions. Although detailed comparisons of the model’s predictions with measured results continue, the present model is a useful tool for GaAs cell design and optimization

Advancement on the Susceptibility of Analog Front-Ends to EMI

L'abstract è presente nell'allegato / the abstract is in the attachmen