Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

Silicon-germanium BiCMOS and silicon-on-insulator CMOS analog circuits for extreme environment applications

Extreme environments pose major obstacles for electronics in the form of extremely wide temperature ranges and hazardous radiation. The most common mitigation procedures involve extensive shielding and temperature control or complete displacement from the environment with high costs in weight, power, volume, and performance. There has been a shift away from these solutions and towards distributed, in-environment electronic systems. However, for this methodology to be viable, the requirements of heavy radiation shielding and temperature control have to be lessened or eliminated. This work gained new understanding of the best practices in analog circuit design for extreme environments. Major accomplishments included the over-temperature -180 C to +120 C and radiation validation of the SiGe Remote Electronics Unit, a first of its kind, 16 channel, sensor interface for unshielded operation in the Lunar environment, the design of two wide-temperature (-180 C to +120 C), total-ionizing-dose hardened, wireline transceivers for the Lunar environment, the low-frequency-noise characterization of a second-generation BiCMOS process from 300 K down to 90 K, the explanation of the physical mechanisms behind the single-event transient response of cascode structures in a 45 nm, SOI, radio-frequency, CMOS technology, the analysis of the single-event transient response of differential structures in a 32 nm, SOI, RF, CMOS technology, and the prediction of scaling trends of single-event effects in SOI CMOS technologies.Ph.D

Modeling of Total Ionizing Dose Effects in Advanced Complementary Metal-Oxide-Semiconductor Technologies

abstract: The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.Dissertation/ThesisPh.D. Electrical Engineering 201

The effects of process variations on performance and robustness of bulk CMOS and SOI implementations of C-elements

Advances in semiconductor technology have been driven by the continuous demands of market forces for IC products with higher performance and greater functionality per unit area. To date industry has addressed these demands, principally, by scaling down device dimensions. However, several unintended consequences have undermined the benefits obtained from the advances in technology, firstly, the growing impact of process variations on interconnectivity delay, aggravated by the increase in the amount of interconnectivity as circuit complexity increases. Overall, the difficulty of establishing delay parameters in a circuit is adversely impacting on the attainment of the timing closure for a design. Secondly, the increase in the susceptibility of the circuits , even at ground level, to the effects of soft errors due to the reduction in supply voltages and nodal capacitances, together with the increase in the number of nodes in a circuit as the functionality per unit area increases. The aim of this research has been to model and analyse the reliability of logic circuits with regard to the impact of process variations and soft errors, and to finds ways to minimise these effects using different process technologies such as fully depleted silicon on insulator (FDSOI) and partially depleted silicon on insulator (PDSOI) technologies, together with the implementation of different circuit architectures. In view of the increased susceptibility of logic elements to the effects of process variations and soft errors as device geometries are reduced, a logic element which is not only widely used but also typical to asynchronous design is the Muller C-element, which can be realised in a number of different circuit configurations. The robustness of various C-element configurations implemented in different technologies with regard to the effects of process variations and soft errors was examined using the design of the experiment (DoE) and response surface (RSM) techniques. It was found that the circuits based on SOI technology were more robust compared with bulk silicon technology. On the other hand, from the circuit architecture perspective, the differential logic implementations of C-element were found to be more resilient to the effects of process variation and soft errors in comparison with the other C-element implementations investigated.EThOS - Electronic Theses Online ServiceMutah UniversityGBUnited Kingdo

The effects of process variations on performance and robustness of bulk CMOS and SOI implementations of C-elements

Advances in semiconductor technology have been driven by the continuous demands of market forces for IC products with higher performance and greater functionality per unit area. To date industry has addressed these demands, principally, by scaling down device dimensions. However, several unintended consequences have undermined the benefits obtained from the advances in technology, firstly, the growing impact of process variations on interconnectivity delay, aggravated by the increase in the amount of interconnectivity as circuit complexity increases. Overall, the difficulty of establishing delay parameters in a circuit is adversely impacting on the attainment of the timing closure for a design. Secondly, the increase in the susceptibility of the circuits , even at ground level, to the effects of soft errors due to the reduction in supply voltages and nodal capacitances, together with the increase in the number of nodes in a circuit as the functionality per unit area increases. The aim of this research has been to model and analyse the reliability of logic circuits with regard to the impact of process variations and soft errors, and to finds ways to minimise these effects using different process technologies such as fully depleted silicon on insulator (FDSOI) and partially depleted silicon on insulator (PDSOI) technologies, together with the implementation of different circuit architectures. In view of the increased susceptibility of logic elements to the effects of process variations and soft errors as device geometries are reduced, a logic element which is not only widely used but also typical to asynchronous design is the Muller C-element, which can be realised in a number of different circuit configurations. The robustness of various C-element configurations implemented in different technologies with regard to the effects of process variations and soft errors was examined using the design of the experiment (DoE) and response surface (RSM) techniques. It was found that the circuits based on SOI technology were more robust compared with bulk silicon technology. On the other hand, from the circuit architecture perspective, the differential logic implementations of C-element were found to be more resilient to the effects of process variation and soft errors in comparison with the other C-element implementations investigated.EThOS - Electronic Theses Online ServiceMutah UniversityGBUnited Kingdo

Investigation of radiation-hardened design of electronic systems with applications to post-accident monitoring for nuclear power plants

This research aims at improving the robustness of electronic systems used-in high level radiation environments by combining with radiation-hardened (rad-hardened) design and fault-tolerant techniques based on commercial off-the-shelf (COTS) components. A specific of the research is to use such systems for wireless post-accident monitoring in nuclear power plants (NPPs). More specifically, the following methods and systems are developed and investigated to accomplish expected research objectives: analysis of radiation responses, design of a radiation-tolerant system, implementation of a wireless post-accident monitoring system for NPPs, performance evaluation without repeat physical tests, and experimental validation in a radiation environment. A method is developed to analyze ionizing radiation responses of COTS-based devices and circuits in various radiation conditions, which can be applied to design circuits robust to ionizing radiation effects without repeated destructive tests in a physical radiation environment. Some mathematical models of semiconductor devices for post-irradiation conditions are investigated, and their radiation responses are analyzed using Technology Computer Aided Design (TCAD) simulator. Those models are then used in the analysis of circuits and systems under radiation condition. Based on the simulation results, method of rapid power off may be effectively to protect electronic systems under ionizing radiation. It can be a potential solution to mitigate damages of electronic components caused by radiation. With simulation studies of photocurrent responses of semiconductor devices, two methods are presented to mitigate the damages of total ionizing dose: component selection and radiation shielding protection. According to the investigation of radiation-tolerance of regular COTS components, most COTS-based semiconductor components may experience performance degradation and radiation damages when the total dose is greater than 20 K Rad (Si). A principle of component selection is given to obtain the suitable components, as well as a method is proposed to assess the component reliability under radiation environments, which uses radiation degradation factors, instead of the usual failure rate data in the reliability model. Radiation degradation factor is as the input to describe the radiation response of a component under a total radiation dose. In addition, a number of typical semiconductor components are also selected as the candidate components for the application of wireless monitoring in nuclear power plants. On the other hand, a multi-layer shielding protection is used to reduce the total dose to be less than 20 K Rad (Si) for a given radiation condition; the selected semiconductor devices can then survive in the radiation condition with the reduced total dose. The calculation method of required shielding thickness is also proposed to achieve the design objectives. Several shielding solutions are also developed and compared for applications in wireless monitoring system in nuclear power plants. A radiation-tolerant architecture is proposed to allow COTS-based electronic systems to be used in high-level radiation environments without using rad-hardened components. Regular COTS components are used with some fault-tolerant techniques to mitigate damages of the system through redundancy, online fault detection, real-time preventive remedial actions, and rapid power off. The functions of measurement, processing, communication, and fault-tolerance are integrated locally within all channels without additional detection units. A hardware emulation bench with redundant channels is constructed to verify the effectiveness of the developed radiation-tolerant architecture. Experimental results have shown that the developed architecture works effectively and redundant channels can switch smoothly in 500 milliseconds or less when a single fault or multiple faults occur. An online mechanism is also investigated to timely detect and diagnose radiation damages in the developed redundant architecture for its radiation tolerance enhancement. This is implemented by the built-in-test technique. A number of tests by using fault injection techniques have been carried out in the developed hardware emulation bench to validate the proposed detection mechanism. The test results have shown that faults and errors can be effectively detected and diagnosed. For the developed redundant wireless devices under given radiation dose (20 K Rad (Si)), the fault detection coverage is about 62.11%. This level of protection could be improved further by putting more resources (CPU consumption, etc.) into the function of fault detection, but the cost will increase. To apply the above investigated techniques and systems, under a severe accident condition in a nuclear power plant, a prototype of wireless post-accident monitoring system (WPAMS) is designed and constructed. Specifically, the radiation-tolerant wireless device is implemented with redundant and diversified channels. The developed system operates effectively to measure up-to-date information from a specific area/process and to transmit that information to remote monitoring station wirelessly. Hence, the correctness of the proposed architecture and approaches in this research has been successfully validated. In the design phase, an assessment method without performing repeated destructive physical tests is investigated to evaluate the radiation-tolerance of electronic systems by combining the evaluation of radiation protection and the analysis of the system reliability under the given radiation conditions. The results of the assessment studies have shown that, under given radiation conditions, the reliability of the developed radiation-tolerant wireless system can be much higher than those of non-redundant channels; and it can work in high-level radiation environments with total dose up to 1 M Rad (Si). Finally, a number of total dose tests are performed to investigate radiation effects induced by gamma radiation on distinct modern wireless monitoring devices. An experimental setup is developed to monitor the performance of signal measurement online and transmission of the developed distinct wireless electronic devices directly under gamma radiator at The Ohio State University Nuclear Reactor Lab (OSU-NRL). The gamma irradiator generates dose rates of 20 K Rad/h and 200 Rad/h on the samples, respectively. It was found that both measurement and transmission functions of distinct wireless measurement and transmission devices work well under gamma radiation conditions before the devices permanently damage. The experimental results have also shown that the developed radiation-tolerant design can be applied to effectively extend the lifespan of COTS-based electronic systems in the high-level radiation environment, as well as to improve the performance of wireless communication systems. According to testing results, the developed radiation-tolerant wireless device with a shielding protection can work at least 21 hours under the highest dose rate (20 K Rad/h). In summary, this research has addressed important issues on the design of radiation-tolerant systems without using rad-hardened electronic components. The proposed methods and systems provide an effective and economical solution to implement monitoring systems for obtaining up-to-date information in high-level radiation environments. The reported contributions are of significance both academically and in practice

GeSn semiconductor for micro-nanoelectronic applications

Within the last few years the steady electronic evolution lead the semiconductor world to study innovative device architectures and new materials able to replace Si platforms. In this scenario Ge1-xSnx alloy attracts the interest of the scientific community due to its ability to tune the material bandgap as a function of Sn content and its extreme compatibility with Si processing. Although the enhanced optical properties of Ge1-xSnx are evident, the augmented electrical properties such as the higher electron and holes mobility are also beneficial for metal oxide semiconductor. Therefore the alloy is expected to be a potential solution to integrate both electrical and optical devices. On one hand, several theoretical and experimental works depict the Ge1-xSnx alloy as a novel and fascinating solution to replace Si; on the other hand the material novelty forces us to enhance the knowledge of its fundamental physical and chemical properties, re-adapting the processing steps necessary to develop electronic and optical devices. In this dissertation a comprehensive study on Ge1-xSnx has been undertaken and discussed analysing a wide range of topics. The first chapter provides a detailed theoretical study on the electronic properties of the GeSn performed using first principle methods; subsequently the data obtained have been inserted into a TCAD software in order to create and calibrate a library used to simulate electrical devices. It is important to note, that at the beginning of this PhD GeSn was not an available material in the Synopsys device software, and thus it had to be defined from scratch As a next point, since the ever decreasing device size push toward the definition of Ohmic contacts, different stanogermanide films have been thoroughly analysed using various metals (Ni, Pt and Ti) annealed with two distinct methodologies (Rapid Thermal Annealing and Laser Thermal Annealing). Subsequently, considering the material limitation such as the limited thermal budget and the Sn segregation, an exhaustive study on the material doping has been firstly discussed theoretically and after experimentally characterized using both classical ion implantation and layer deposition techniques. The different building blocks of Field Effect Transistors have been investigated and tuned individually with the aim to develop FET devices with bottom up approach. Then, Field Effect Transistor devices using GeSn NWs grown by a VLS methodology with Sn composition ranging from (0.03-0.09 at.%) have been developed and extensively characterized with the state of the art present in literature. Finally the analysis of highly selective etch recipes lead to the development of sub-nm device configuration such as Gate-All-Around (GAA) structure obtained using classical top down lithography approach. The innovative structure was electrically characterized highlighting the possibility to obtain decananometer device architecture with this innovative alloy. Lastly thesis summary and final outlooks were reported with the aim to outline the thesis contribution and the future material investigations