Quantitative Decoding of Interactions in Tunable Nanomagnet Arrays Using First Order Reversal Curves

To develop a full understanding of interactions in nanomagnet arrays is a persistent challenge, critically impacting their technological acceptance. This paper reports the experimental, numerical and analytical investigation of interactions in arrays of Co nanoellipses using the first-order reversal curve (FORC) technique. A mean-field analysis has revealed the physical mechanisms giving rise to all of the observed features: a shift of the non-interacting FORC-ridge at the low-H$_c$ end off the local coercivity H$_c$ axis; a stretch of the FORC-ridge at the high-H$_c$ end without shifting it off the H$_c$ axis; and a formation of a tilted edge connected to the ridge at the low-H$_c$ end. Changing from flat to Gaussian coercivity distribution produces a negative feature, bends the ridge, and broadens the edge. Finally, nearest neighbor interactions segment the FORC-ridge. These results demonstrate that the FORC approach provides a comprehensive framework to qualitatively and quantitatively decode interactions in nanomagnet arrays.Comment: 19 pages, 4 figures. 9 page supplemental material including 3 figure

An all monolithic MOS A/D converter - Low power clocks, multiplexers, registers, and A/D converter Final report

Research and developments of monolithic, MOS, ten bit, analog to digital converte

Engineering study for a mass memory system for advanced spacecrafts Final report, 1 Dec. 1969 - 1 Jul. 1970

Mass memory system for advanced spacecraf

Quantum computing with neutral atoms

We develop a method to entangle neutral atoms using cold controlled collisions. We analyze this method in two particular set-ups: optical lattices and magnetic micro-traps. Both offer the possibility of performing certain multi-particle operations in parallel. Using this fact, we show how to implement efficient quantum error correction and schemes for fault-tolerant computing.Comment: 21 pages, 19 figure

An investigation of potential applications of OP-SAPS: Operational Sampled Analog Processors

The application of OP-SAP's (operational sampled analog processors) in pattern recognition system is summarized. Areas investigated include: (1) human face recognition; (2) a high-speed programmable transversal filter system; (3) discrete word (speech) recognition; and (4) a resolution enhancement system

Decoding LDPC Codes with Probabilistic Local Maximum Likelihood Bit Flipping

Communication channels are inherently noisy making error correction coding a major topic of research for modern communication systems. Error correction coding is the addition of redundancy to information transmitted over communication channels to enable detection and recovery of erroneous information. Low-density parity-check (LDPC) codes are a class of error correcting codes that have been effective in maintaining reliability of information transmitted over communication channels. Multiple algorithms have been developed to benefit from the LDPC coding scheme to improve recovery of erroneous information. This work develops a matrix construction that stores the information error probability statistics for a communication channel. This combined with the error correcting capability of LDPC codes enabled the development of the Probabilistic Local Maximum Likelihood Bit Flipping (PLMLBF) algorithm, which is the focus of this research work

Self-Healing Cellular Automata to Correct Soft Errors in Defective Embedded Program Memories

Static Random Access Memory (SRAM) cells in ultra-low power Integrated Circuits (ICs) based on nanoscale Complementary Metal Oxide Semiconductor (CMOS) devices are likely to be the most vulnerable to large-scale soft errors. Conventional error correction circuits may not be able to handle the distributed nature of such errors and are susceptible to soft errors themselves. In this thesis, a distributed error correction circuit called Self-Healing Cellular Automata (SHCA) that can repair itself is presented. A possible way to deploy a SHCA in a system of SRAM-based embedded program memories (ePM) for one type of chip multi-processors is also discussed. The SHCA is compared with conventional error correction approaches and its strengths and limitations are analyzed

Multipac, a multiple pool processor and computer for a spacecraft central data system

Spacecraft central data system computer used on deep space probe