7 research outputs found
Chip- and System-Level Reliability on SiC-based Power Modules
The blocking voltage, switching frequency and temperature tolerance of power devices have been greatly improved due to the revolution of wide bandgap (WBG) materials, such as silicon carbide (SiC) and gallium nitride (GaN). Owing to the development of SiC-based power devices, the power rating, operating voltage, and power density of power modules have been significantly improved. However, the reliability of SiC-based power modules has not been fully explored yet. Thus, this dissertation focuses on the chip- and system-level reliability on SiC-based power modules. For chip-level reliability, this work focuses on on-chip SiC ESD protection devices for SiC-based integrated circuits (ICs). In order to develop SiC ESD protection devices, SiC-based Ohmic contact and ion implantation have been studied. Nickel/Titanium/Aluminum (Ni/Ti/Al) metal stacks were deposited on SiC substrates to form Ohmic contact. Circular transfer length method (CTLM) structures were fabricated to characterize contact resistivity. Ion implantation was designed and simulated by Sentraurus technology computer aided design (TCAD) software. Secondary-ion mass spectrometry (SIMS) results show a good match with the simulation results. In addition, SiC ESD protection devices, such as N-type metal-oxide-semiconductor (NMOS), laterally diffused metal-oxide-semiconductor (LDMOS), high-voltage silicon controlled rectifier (HV-SCR) and low-voltage silicon controlled rectifier (LV-SCR), have been designed. Transmission line pulse (TLP) and very fast TLP (VF-TLP) measurements were carried out to characterize their ESD performance. The proposed SiC-based HV-SCR shows the highest failure current on TLP measurement and can be used as an area-efficient ESD protection device. On the other hand, for system-level reliability, this dissertation focuses on the galvanic isolation of high-temperature SiC power modules. Low temperature co-fired ceramics (LTCC) based high-temperature optocouplers were designed and fabricated as galvanic isolators. The LTCC-based high-temperature optocouplers show promising driving capability and steady response speed from 25 ÂșC to 250 ÂșC. In order to verify the performance of the high-temperature optocouplers at the system level, LTCC-based gate drivers that utilize the high-temperature optocouplers as galvanic isolators were designed and integrated into a high-temperature SiC-based power module. Finally, the high-temperature power module with integrated LTCC-based gate drivers was characterized by DPTs from 25 ÂșC to 200 ÂșC. The power module shows reliable switching performance at elevated temperatures
Chip- and System-Level Reliability on SiC-based Power Modules
The blocking voltage, switching frequency and temperature tolerance of power devices have been greatly improved due to the revolution of wide bandgap (WBG) materials, such as silicon carbide (SiC) and gallium nitride (GaN). Owing to the development of SiC-based power devices, the power rating, operating voltage, and power density of power modules have been significantly improved. However, the reliability of SiC-based power modules has not been fully explored yet. Thus, this dissertation focuses on the chip- and system-level reliability on SiC-based power modules. For chip-level reliability, this work focuses on on-chip SiC ESD protection devices for SiC-based integrated circuits (ICs). In order to develop SiC ESD protection devices, SiC-based Ohmic contact and ion implantation have been studied. Nickel/Titanium/Aluminum (Ni/Ti/Al) metal stacks were deposited on SiC substrates to form Ohmic contact. Circular transfer length method (CTLM) structures were fabricated to characterize contact resistivity. Ion implantation was designed and simulated by Sentraurus technology computer aided design (TCAD) software. Secondary-ion mass spectrometry (SIMS) results show a good match with the simulation results. In addition, SiC ESD protection devices, such as N-type metal-oxide-semiconductor (NMOS), laterally diffused metal-oxide-semiconductor (LDMOS), high-voltage silicon controlled rectifier (HV-SCR) and low-voltage silicon controlled rectifier (LV-SCR), have been designed. Transmission line pulse (TLP) and very fast TLP (VF-TLP) measurements were carried out to characterize their ESD performance. The proposed SiC-based HV-SCR shows the highest failure current on TLP measurement and can be used as an area-efficient ESD protection device. On the other hand, for system-level reliability, this dissertation focuses on the galvanic isolation of high-temperature SiC power modules. Low temperature co-fired ceramics (LTCC) based high-temperature optocouplers were designed and fabricated as galvanic isolators. The LTCC-based high-temperature optocouplers show promising driving capability and steady response speed from 25 ÂșC to 250 ÂșC. In order to verify the performance of the high-temperature optocouplers at the system level, LTCC-based gate drivers that utilize the high-temperature optocouplers as galvanic isolators were designed and integrated into a high-temperature SiC-based power module. Finally, the high-temperature power module with integrated LTCC-based gate drivers was characterized by DPTs from 25 ÂșC to 200 ÂșC. The power module shows reliable switching performance at elevated temperatures
Structures MOS-IGBT sur technologie SOI en vue de l'amélioration des performances à haute température de composants de puissance et de protections ESD
Dans le cadre du projet FNRAE COTECH, nos travaux avaient pour objectifs d'amĂ©liorer le fonctionnement des structures Ă©lectroniques Ă haute tempĂ©rature d'une technologie SOI (200°C). La technologie choisie pour ce travail est une technologie de puissance intelligente comprenant une bibliothĂšque CMOS basse tension (5V), des transistors de puissance LDMOS (25V, 45V et 80V) et des transistors bipolaires NPN et PNP. Afin de caractĂ©riser cette technologie en tempĂ©rature, dans un premier temps, nous avons conçu un vĂ©hicule de test en introduisant certaines rĂšgles de dessin bĂ©nĂ©fiques pour le comportement en tempĂ©rature, Ă la fois pour les composants basse et haute puissance. Nous avons Ă©galement Ă©tudiĂ© une nouvelle architecture de composants combinant au sein d'un mĂȘme composant un composant MOS et un composant IGBT, dans un objectif d'auto-compensation des effets nĂ©gatifs de la tempĂ©rature. Afin d'optimiser la conception de ces composants mixtes MOS-IGBT, la mĂ©thodologie que nous avons adoptĂ©e s'est appuyĂ©e sur des simulations 2D et 3D sur Sentaurus. Dans le cadre de ce travail, deux vĂ©hicules de test ont Ă©tĂ© rĂ©alisĂ©s et caractĂ©risĂ©s. Ces structures mixtes MOS-IGBT ont Ă©tĂ© proposĂ©es en tant que structures de protection contre les dĂ©charges Ă©lectrostatiques (ESD) pour remplacer une structure de protection de type "power clamp". En s'appuyant sur la simulation 3D, nous avons proposĂ© plusieurs solutions, Ă la fois topologiques et d'architecture, permettant d'augmenter significativement le niveau de ce courant. Ces diverses solutions ont Ă©tĂ© validĂ©es expĂ©rimentalement. Enfin, les bonnes performances de ces structures mixtes ont motivĂ© leur Ă©tude en tant que structures de puissance.Within the framework of COTECH FNRAE project, the objectives of our work were the improvement of the SOI electronic structures at high-temperature operation (200°C). The chosen technology in this work is a smart power technology including low voltage CMOS (5 V), LDMOS power transistors (25 V, 45 V and 80 V), NPN and PNP bipolar transistor. To characterize this technology at different temperatures, as a first step, we designed a test vehicle by introducing specific design rules beneficial for the temperature behavior, both for low and high power components. We also studied new components architecture by combining in a single component a MOS and an IGBT, with an objective of self-compensation of the negative effects of temperature. To optimize the performance of these components (mixed MOS-IGBT), our methodology was based on using 2D and 3D Sentaurus physical simulation. As part of this work, two test vehicles were produced and characterized. These mixed structures MOS-IGBT have been proposed as ESD protection structures (Electro Static Discharge protection structures), to replace the LDMOS of a power clamp circuit. Based on 3D simulation, we have proposed several solutions, both topological and architectural, to significantly increase the level of the holding current. These various solutions have been experimentally validated. Finally, the good performance of these mixed structures have motivated their study as power structures
Semiconductor Device Modeling, Simulation, and Failure Prediction for Electrostatic Discharge Conditions
Electrostatic Discharge (ESD) caused failures are major reliability issues in IC industry. Device modeling for ESD conditions is necessary to evaluate ESD robustness in simulation. Although SPICE model is accurate and efficient for circuit simulations in most cases, devices under ESD conditions operate in abnormal status. SPICE model cannot cover the device operating region beyond normal operation. Thermal failure is one of the main reasons to cause device failure under ESD conditions. A compact model is developed to predict thermal failure with circuit simulators. Instead of considering the detailed failure mechanisms, a failure temperature is introduced to indicate device failure. The developed model is implemented by a multiple-stage thermal network. P-N junction is the fundamental structure for ESD protection devices. An enhanced diode model is proposed and is used to simulate the device behaviors for ESD events. The model includes all physical effects for ESD conditions, which are voltage overshoot, self-heating effect, velocity saturation and thermal failure. The proposed model not only can fit the I-V and transient characteristics, but also can predict failure for different pulses. Safe Operating Area (SOA) is an important factor to evaluate the LDMOS performance. The transient SOA boundary is considered as power-defined. By placing the failure monitor under certain conditions, the developed modeling methodology can predict the boundary of transient SOA for any short pulse stress conditions. No matter failure happens before or after snapback phenomenon. Weibull distribution is popular to evaluate the dielectric lifetime for CVS. By using the transformative version of power law, the pulsing stresses are converted into CVS, and TDDB under ESD conditions for SiN MIMCAPs is analyzed. The thickness dependency and area independency of capacitor breakdown voltage is observed, which can be explained by the constant ?E model instead of conventional percolation model
Design of Novel Devices and Circuits for Electrostatic Discharge Protection Applications in Advanced Semiconductor Technologies
Electrostatic Discharge (ESD), as a subset of Electrical Overstress (EOS), was reported to be in charge of more than 35% of failure in integrated circuits (ICs). Especially in the manufacturing process, the silicon wafer turns out to be a functional ICs after numerous physical, chemical and mechanical processes, each of which expose the sensitive and fragile ICs to ESD environment. In normal end-user applications, ESD from human and machine handling, surge and spike signals in the power supply, and wrong supplying signals, will probably cause severe damage to the ICs and even the whole systems. Generally, ESD protections are evaluated after wafer and even system fabrication, increasing the development period and cost if the protections cannot meet customer\u27s requirements. Therefore, it is important to design and customize robust and area-efficient ESD protections for the ICs at the early development stage. As the technologies generally scaling down, however, ESD protection clamps remain comparable area consumption in the recent years because they provide the discharging path for the ESD energy which rarely scales down. Diode is the most simple and effective device for ESD protection in ICs, but the usage is significantly limited by its low turn-on voltage. MOS devices can be triggered by a dynamic-triggered RC circuit for IOs operating at low voltage, while the one triggered by a static-triggered network, e.g., zener-resistor circuit or grounded-gate configuration, provides a high trigger voltage for high-voltage applications. However, the relatively low current discharging capability makes MOS devices as the secondary choice. Silicon-controlled rectifier (SCR) has become famous due to its high robustness and area efficiency, compared to diode and MOS. In this dissertation, a comprehensive design methodology for SCR based on simulation and measurement are presented for different advanced commercial technologies. Furthermore, an ESD clamp is designed and verified for the first time for the emerging GaN technology. For the SCR, no matter what modification is going to be made, the first concern when drawing the layout is to determine the layout geometrical style, finger width and finger number. This problem for diode and MOS device were studied in detail, so the same method was usually used in SCR. The research in this dissertation provides a closer look into the metal layout effect to the SCR, finding out the optimized robustness and minimized side-effect can be obtained by using specific layout geometry. Another concern about SCR is the relatively low turn-on speed when the IOs under protection is stressed by ESD pulses having very fast rising time, e.g., CDM and IEC 61000-4-2 pulses. On this occasion a large overshoot voltage is generated and cause damage to internal circuit component like gate oxides of MOS devices. The key determination of turn-on speed of SCR is physically investigated, followed by a novel design on SCR by directly connecting the Anode Gate and Cathode Gate to form internal trigger (DCSCR), with improved performance verified experimentally in this dissertation. The overshoot voltage and trigger voltage of the DCSCR will be significantly reduced, in return a better protection for internal circuit component is offered without scarifying neither area or robustness. Even though two SCR\u27s with single direction of ESD current path can be constructed in reverse parallel to form bidirectional protection to pins, stand-alone bidirectional SCR (BSCR) is always desirable for sake of smaller area. The inherent high trigger voltage of BSCR that only fit in high-voltage technologies is overcome by embedding a PMOS transistor as trigger element, making it highly suitable for low-voltage ESD protection applications. More than that, this modification simultaneously introduces benefits including high robustness and low overshoot voltage. For high voltage pins, however, it presents another story for ESD designs. The high operation voltages require that a high trigger voltage and high holding voltage, so as to reduce the false trigger and latch-up risk. For several capacitive pins, the displacement current induced by a large snapback will cause severe damage to internal circuits. A novel design on SCR is proposed to minimize the snapback with adjustable trigger and holding voltage. Thanks to the additional a PIN diode, the similar high robustness and stable thermal leakage performance to SCR is maintained. For academic purpose of ESD design, it is always difficult to obtain the complete process deck in TCAD simulation because those information are highly confidential to the companies. Another challenge of using TCAD is the difficulty of maintaining the accuracy of physics models and predicting the performance of the other structures. In this dissertation a TCAD-aid ESD design methodology is used to evaluate ESD performance before the silicon shuttle. GaN is a promising material for high-voltage high-power RF application compared to the GaAs. However, distinct from GaAs, the leaky problem of the schottky junction and the lack of choice of passive/active components in GaN technology limit the ESD protection design, which will be discussed in this dissertation. However, a promising ESD protection clamp is finally developed based on depletion-mode pHEMT with adjustable trigger voltage, reasonable leakage current and high robustness
Design of Low-Capacitance Electrostatic Discharge (ESD) Protection Devices in Advanced Silicon Technologies.
Electrostatic discharge (ESD) related failure is a major IC reliability concern and this is particularly true as technology continues shrink to nano-metric dimensions. ESD design window research shows that ESD robustness of victim devices keep decreasing from 350nm bulk technology to 7nm FinFET technologies. In the meantime, parasitic capacitance of ESD diode with same It2 in FinFET technologies is approximately 3X compared with that in planar technologies. Thus transition from planar to FinFET technology requires more robust ESD protection however the large parasitic capacitance of ESD protection cell is problematic in high-speed interface design. To reduce the parasitic capacitance, a dual diode silicon controlled rectifier (DD-SCR) is presented in this dissertation. This design can exhibit good trade-offs between ESD robustness and parasitic capacitance characteristics. Besides, different bounding materials lead to performance variations in DD-SCRs are compared. Radio frequency (RF) technology is also demanded low capacitance ESD protection. To address this concern, a ?-network is presented, providing robust ESD protection for 10-60 GHz RF circuit. Like a low pass ? filter, the network can reflect high frequency RF signals and transmit low frequency ESD pulses. Given proper inductor value, networks can work as robust ESD solutions at a certain Giga Hertz frequency range, making this design suitable for broad band protection in RF input/outputs (I/Os). To increase the holding voltage and reduce snapback, a resistor assist triggering heterogeneous stacking structure is presented in this dissertation, which can increase the holding voltage and also keep the trigger voltage nearly as same as a single SCR device
Optimization and Modelling of Semiconductor Devices in a 0.35 ”m CMOS High Temperature Technology
Die vorliegende Arbeit beschĂ€ftigte sich mit der Optimierung und Modellierung von Bauelementen in einer 0,35 ÎŒm-CMOS-Technologie, die speziell fĂŒr den Betrieb in einem erweiterten Temperaturbereich von â40 â bis 250 â vorgesehen ist. Bei dieser Technologie handelt es sich um eine Weiterentwicklung einer 1 ÎŒm-Technologie, die in weiten Teilen der Prozessierung modifiziert wurde. Durch die geringe Strukturbreite lassen sich komplexere Schaltungen und eine höhere Packungsdichte realisieren. Die Herstellung erfolgt in einer DĂŒnnfilm-SOI-Technologie, die gegenĂŒber einer ĂŒblicherweise verwendeten Bulk-Technologie deutliche Vorteile beim Hochtemperaturbetrieb bietet.
Die zahlreichen VerĂ€nderungen in der neuen Technologie erforderten zunĂ€chst die Anpassung des elektrischen Verhaltens verschiedener Bauelemente an die gesetzten Spezifikationen. Dazu gehörte die Charakterisierung und die Parameterextraktion des verkleinerten Transistortyps. Die Optimierung des Durchbruchverhaltens einer Diode, die zum Schutz vor Ăberspannungspulsen eingesetzt wird, konnte durch die Anpassung der Dotierstoffkonzentrationen erreicht werden. Ebenfalls konnte eine Steigerung der Spannungsfestigkeit eines Hochspannungstransistors erzielt werden, indem u. a. der Avalanche-Effekt durch einen besseren Kanalanschluss vermieden wurde. Neben der Optimierung des elektrischen Verhaltens wurde auch das ZuverlĂ€ssigkeitsverhalten der Bauelemente verbessert. Hierzu gehörte die Optimierung der OxidqualitĂ€t, welche durch Getterung von Kontaminationsatomen signifikant gesteigert werden konnte. Weiterhin konnte auch das ZuverlĂ€ssigkeitsverhalten der Speicherzellen (EEPROM), welches durch die beiden Aspekte der DatenwechselstabilitĂ€t und des Datenerhalts beschrieben wird, durch geometrische VerĂ€nderungen und Abschirmung der Zelle verbessert werden.
Ein weiterer wichtiger Aspekt dieser Arbeit war die Entwicklung von Simulationsmodellen bestimmter Bauelemente in einem breiten Temperaturbereich. Zum einen konnte das elektrische Verhalten von Dioden bei Temperaturen zwischen â40 â und 300 â durch ein Makromodell genau nachgebildet werden. Zum anderen konnten die DatenwechselstabilitĂ€t und der Datenerhalt der Speicherzelle bis zu einer Temperatur von 450 â mithilfe eines Modells korrekt wiedergegeben werden. Die Modelle werden verwendet, um eine Vorhersage ĂŒber das Verhalten von Bauelementen bei unterschiedlichen Temperaturen zu treffen, dienen als Hilfsmittel zur Optimierung der Bauelemente und sind fĂŒr die Simulation von Schaltungen notwendig.
Weiterhin wurden in der vorliegenden Arbeit neue Bauelemente vorgestellt, die vor allem fĂŒr den Einsatz in einem breiten Temperaturbereich konzipiert sind. So wurde eine Schutzstruktur vor Ăberspannungspulsen vorgeschlagen, die bei einer Betriebsspannung von 3,3 V und einer Temperatur bis 250 â eingesetzt werden soll. Dazu wurde entweder der Punch-Through- oder der Floating-Body-Effekt ausgenutzt, um das Bauelement ab einer bestimmten Spannung in den Leitungszustand zu versetzen. FĂŒr den Betrieb eines Hochspannungstransistors wurde in dieser Arbeit eine Bauweise vorgeschlagen, die es ermöglicht, die transistorspezifischen Eigenschaften, wie die Schwellenspannung oder den Leckstrom, in AbhĂ€ngigkeit der Temperatur deutlich zu verbessern.
Somit wurden in dieser Arbeit verschiedene kritische Bereiche einer CMOS-Technologie behandelt, die sich beim Hochtemperaturbetrieb ergeben. Dazu wurden Optimierungen im Bezug auf das elektrische Verhalten bzw. die ZuverlĂ€ssigkeit vorgeschlagen und neue Bauelemente entwickelt, die vor allem fĂŒr den Betrieb bei hohen Temperaturen ausgelegt sind. ZusĂ€tzlich wurden Simulationsmodelle fĂŒr den erweiterten Temperaturbereich entwickelt, die nicht zuletzt zur Optimierung der Bauelemente beitragen.The present work focuses on the optimization and modeling of devices from a 0.35 ÎŒm technology developed for the operation in a wide temperature range from â40 â up to 250 â. This technology is a further development of a 1 ÎŒm high temperature technology with various modifications in the processing flow. The shrink of the technology node allows to process more complex integrated circuits with a higher device density. For the wide temperature range, a thin film SOI technology is utilized that shows substantial benefits compared to the commonly used bulk technology.
The numerous changes in the new technology require adjustment of the electric behavior of different devices to fulfill the specifications. Within the framework of this study one of the tasks was the characterization and the parameter extraction of the downsized transistor type. Further the breakdown behavior of a diode used for ESD protection was optimized by adapting the doping concentration. The breakdown voltage of a high voltage transistor was enhanced by a proper biasing of the channel area. Besides the optimization of the electric behavior the reliability of the devices was improved as well. For this purpose, the oxide quality was optimized by gettering contaminants. Furthermore the reliability of the memory cells (EEPROM) that can be described by the retention and endurance behavior was increased by geometrical optimization and a better isolation of the cell.
In addition, simulation models were developed for specific devices to characterize the electric behavior in a wide temperature range. The characteristics of two different diodes at temperatures between â40 â and 300 â were simulated by a macro model. The endurance and retention behavior of a memory cell was also described by a macro model for temperatures up to 450 â. The models are used to predict the behavior of the devices at different temperatures, serve as auxiliary tools to optimize the devices and are also used for circuit simulations.
Furthermore, new devices are developed in the present work to enable the operation in a wide temperature range. An ESD device is proposed to protect circuits with a low operating voltage of 3.3 V for temperatures up to 250 â. For this purpose, the punch through or floating body effect is used to bring the device in a conduction state at a certain trigger voltage. For the operation of high voltage transistor a new design is proposed, which allows to improve the transistor specific properties (for example leakage current or threshold voltage) at high temperatures.
In summary, different critical parts of a CMOS technology designed for high temperature applications are investigated in this work. Optimizations with respect to the electric behavior and the reliability are proposed and new devices are developed to improve the performance at high temperatures. Additionally, simulation models are proposed to allow an accurate description of the electrical device behavior in a wide temperature range and which can also be used to optimize the device performance