High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

TOWARDS INTEGRATION OF GRAPHENE IN ADVANCED CMOS INTERCONNECT TECHNOLOGY

The integration of graphene into existing state-of-the-art semiconductor manufacturing is a topic of worldwide interest. With its unprecedented electrical, thermal and mechanical properties, graphene is ideally suited for back-end of line (BEOL) technology to boost the performance of on-chip copper (Cu) interconnects. However, the lack of BEOL compatible methods has stymied the true evaluation of Cu/graphene hybrid (Cu-G) technology. The objectives of this thesis proposal are to demonstrate BEOL-compatible graphene growth techniques, and explore various avenues for practical integration of graphene in order to achieve better electrical, thermal and reliability metrics than traditional interconnect technology

Réalisation, caractérisation et modélisation de nanofils pour application RF

Les composants nano électroniques ont fait l'objet d'intérêt marqué, au sein de la communauté des concepteurs de circuits radiofréquence au cours de ces dernières années. Non seulement ils peuvent présenter des caractéristiques intéressantes, mais ils offrent la perspective d'améliorations de la miniaturisation des composants les plus avancés. Les nanotubes de carbone et les nanofils conducteurs sont attendus comme pouvant potentiellement constituer des blocs utilisables dans les futurs circuits aux très faibles dimensions. Les conducteurs métalliques sont utilisés depuis longtemps pour réaliser des composants passifs dans les circuits intégrés radio fréquence, cependant très peu de travaux ont été menés sur des conducteurs ayant des dimensions nanométriques et fonctionnant dans le domaine millimétrique. L'objectif de cette thèse est d'exploré les propriétés RF de conducteurs métalliques aux dimensions nanométriques et la possibilité de les intégrés dans des circuits utilisant des technologies CMOS. Dans cette thèse, des lignes de transmission et des antennes intégrées sur puce, utilisant des nanofils conducteurs, ont été conçues et réalisées en utilisant un processus de fabrication "top-down". Les caractéristiques en terme de transmission de signal ont été observées expérimentalement dans le domaine millimétrique par la mesure de paramètres S. Deux types de lignes ont été conçus : des lignes micro-ruban de faible épaisseur et des lignes coplanaires. Les caractéristiques en fonction de la fréquence du signal d'excitation ont été analysées. Différents paramètres comme la largeur, l'épaisseur, le nombre de nanofils et la distance entre les nanofils ont été étudiés. De plus, un modèle de propagation basée sur des ondes quasi-TEM a été proposé pour obtenir une compréhension fine du comportement physique des nanofils. Par ailleurs, une étude approfondies concernant les techniques d'épluchage (de-embedding) a été menée afin d'améliorer la précision des mesures. En parallèle, des antennes dipôle et IFA, utilisant des nanofils, ont été réalisées pour tester la transmission sans ligne de propagation. Différentes dimensions de conducteurs et différents types de substrats ont été utilisés pour étudier leurs propriétés et obtenir les meilleures performances.Nano-electronic devices have attracted much attention for the radio frequency engineering community in recent years. They not only exhibit compelling characteristics but show promises to enhance the miniaturization of modern devices. Carbon nanotubes and conducting nanowires are believed to be potential building blocks for ultra-small chip of the future. Metallic wires have long been utilized as the passive components in the RF integrated circuit but there are very few studies on their nanoscale counterpart particularly up to millimeter-wave frequencies. The focus of this thesis is to explore RF properties of metallic nanowires and their potentials to be integrated in CMOS communication technology. In this thesis, transmission lines and on-chip antennas integrated with metallic nanowires were developed enabled by top-down fabrication processes. The signal transmission properties of such devices were characterized well into the mm-wave regime based on two-port S-parameters measurement. Two types of nano-transmission lines were designed: thin film microstrip lines and coplanar waveguides. Their transmission characteristics as a function of frequencies were analysed. Different parameters like the linewidth, thickness, number of nanowires, and the distance between the wires were examined. In addition, a quasi-TEM propagation model was proposed to provide a further insight into the physical behaviours of the nanowires. Moreover, a comprehensive study regarding the de-embedding techniques was carried out in order to improve measurement accuracy. Meanwhile, on-chip dipoles and planar meander-line inverted F antenna were implemented to test the wireless signal transmission of the metallic nanowires. Various wires dimensions and substrates were designed to exploit their characteristics thus facilitating better transmission.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Advanced modelling and design considerations for interconnects in ultra- low power digital system

PhD ThesisAs Very Large Scale Integration (VLSI) is progressing in very Deep submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption for advanced System-on- Chip (SoC)s. However, the growing complexity of interconnects behaviour presents a challenge for their adequate modelling, whereby conventional circuit theoretic approaches cannot provide sufficient accuracy. During the last decades, fractional differential calculus has been successfully applied to modelling certain classes of dynamical systems while keeping complexity of the models under acceptable bounds. For example, fractional calculus can help capturing inherent physical effects in electrical networks in a compact form, without following conventional assumptions about linearization of non-linear interconnect components. This thesis tackles the problem of interconnect modelling in its generality to simulate a wide range of interconnection configurations, its capacity to emulate irregular circuit elements and its simplicity in the form of responsible approximation. This includes modelling and analysing interconnections considering their irregular components to add more flexibility and freedom for design. The aim is to achieve the simplest adaptable model with the highest possible accuracy. Thus, the proposed model can be used for fast computer simulation of interconnection behaviour. In addition, this thesis proposes a low power circuit for driving a global interconnect at voltages close to the noise level. As a result, the proposed circuit demonstrates a promising solution to address the energy and performance issues related to scaling effects on interconnects along with soft errors that can be caused by neutron particles. The major contributions of this thesis are twofold. Firstly, in order to address Ultra-Low Power (ULP) design limitations, a novel driver scheme has been configured. This scheme uses a bootstrap circuitry which boosts the driver’s ability to drive a long interconnect with an important feedback feature in it. Hence, this approach achieves two objectives: improving performance and mitigating power consumption. Those achievements are essential in designing ULP circuits along with occupying a smaller footprint and being immune to noise, observed in this design as well. These have been verified by comparing the proposed design to the previous and traditional circuits using a simulation tool. Additionally, the boosting based approach has been shown beneficial in mitigating the effects of single event upset (SEU)s, which are known to affect DSM circuits working under low voltages. Secondly, the CMOS circuit driving a distributed RLC load has been brought in its analysis into the fractional order domain. This model will make the on-chip interconnect structure easy to adjust by including the effect of fractional orders on the interconnect timing, which has not been considered before. A second-order model for the transfer functions of the proposed general structure is derived, keeping the complexity associated with second-order models for this class of circuits at a minimum. The approach here attaches an important trait of robustness to the circuit design procedure; namely, by simply adjusting the fractional order we can avoid modifying the circuit components. This can also be used to optimise the estimation of the system’s delay for a broad range of frequencies, particularly at the beginning of the design flow, when computational speed is of paramount importance.Iraqi Ministry of Higher Education and Scientific Researc

Radio Frequency Micro/Nano-Fluidic Devices for Microwave Dielectric Property Characterizations

In this dissertation, a number of different topics in microwave dielectric property measurements have been covered by a systematic approach to the goals of development of dielectric spectroscopy and study of its high electric field effects with integrated on-chip microwave microfluidic / nanofluidic devices. A method of parasitic effects cancellation for dielectric property measurement is proposed, analyzed, and experimentally evaluated for microwave characterization of small devices and materials that yield low intensity signals. The method dramatically reduces parasitic effects to uncover the otherwise buried signals. A high-sensitive radio frequency (RF) device is then developed and fabricated to detect small dielectric property changes in microfluidic channel. Sensitivity improvement via on-chip transmission line loss compensation is then analyzed and experimentally demonstrated. Different samples are measured and high sensitivity is achieved compared to conventional transmission-line-based methods. High DC electric field effects on dielectric properties of water are investigated with microwave microfluidic devices. Gold microstrip-line-based devices and highly-doped silicon microstrip-line-based devices are exploited. Initiation process of water breakdown in a small gap is discussed. Electrode surface roughness is examined and its effect on observed water breakdown is investigated. It is believed that electrode surface roughness is one of critical factors for the initiation process of water breakdown in small gap system. Finally, water dielectric property subjected to uniform DC electric field in 260 nm planar microfluidic channels is experimentally studied via silicon microstrip-line-based devices. When applied DC field is as high as up to ~ 1 MV/cm, the water is sustained and no breakdown is occurred. Strong water dielectric saturation effects are observed from measured water dielectric spectroscopy. An on-chip, broadband microwave dielectric spectrometer with integrated transmission line and nanofluidic channels is designed, fabricated and characterized through microwave S-parameter measurements. Heavily-doped Si material is used to build the microstrip line to provide broadband characterization capability. 10 nm deep planar Si nanofluidic channels are fabricated through native oxide etch and wafer bonding process. It is the first effort to build the microstrip line with periodically loaded individual sub-10 nm nanofluidic channels to conduct the broadband high frequency characterization of materials within confined space. The functionality of the device is demonstrated by the measurement of DI water. It behaves well and has great potentials on the study of confinement effects of fluids and molecules. Further work includes development of parasitic signal de-embedding procedures for accurate measurements

Energy efficient hybrid computing systems using spin devices

Emerging spin-devices like magnetic tunnel junctions (MTJ\u27s), spin-valves and domain wall magnets (DWM) have opened new avenues for spin-based logic design. This work explored potential computing applications which can exploit such devices for higher energy-efficiency and performance. The proposed applications involve hybrid design schemes, where charge-based devices supplement the spin-devices, to gain large benefits at the system level. As an example, lateral spin valves (LSV) involve switching of nanomagnets using spin-polarized current injection through a metallic channel such as Cu. Such spin-torque based devices possess several interesting properties that can be exploited for ultra-low power computation. Analog characteristic of spin current facilitate non-Boolean computation like majority evaluation that can be used to model a neuron. The magneto-metallic neurons can operate at ultra-low terminal voltage of ∼20mV, thereby resulting in small computation power. Moreover, since nano-magnets inherently act as memory elements, these devices can facilitate integration of logic and memory in interesting ways. The spin based neurons can be integrated with CMOS and other emerging devices leading to different classes of neuromorphic/non-Von-Neumann architectures. The spin-based designs involve `mixed-mode\u27 processing and hence can provide very compact and ultra-low energy solutions for complex computation blocks, both digital as well as analog. Such low-power, hybrid designs can be suitable for various data processing applications like cognitive computing, associative memory, and currentmode on-chip global interconnects. Simulation results for these applications based on device-circuit co-simulation framework predict more than ∼100x improvement in computation energy as compared to state of the art CMOS design, for optimal spin-device parameters

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

The Development of Novel Interconnection Technologies for 3D Packaging of Wire Bondless Silicon Carbide Power Modules

This dissertation advances the cause for the 3D packaging and integration of silicon carbide power modules. 3D wire bondless approaches adopted for enhancing the performance of silicon power modules were surveyed, and their merits were assessed to serve as a vision for the future of SiC power packaging. Current efforts pursuing 3D wire bondless SiC power modules were investigated, and the concept for a novel SiC power module was discussed. This highly-integrated SiC power module was assessed for feasibility, with a focus on achieving ultralow parasitic inductances in the critical switching loops. This will enable higher switching frequencies, leading to a reduction in the size of the passive devices in the system and resulting in systems with lower weight and volume. The proposed concept yielded an order-of-magnitude reduction in system parasitics, alongside the possibility of a compact system integration. The technological barriers to realizing these concepts were identified, and solutions for novel interconnection schemes were proposed and evaluated. A novel sintered silver preform was developed to facilitate flip-chip interconnections for a bare-die power device while operating in a high ambient temperature. The preform was demonstrated to have 3.75× more bonding strength than a conventional sintered silver bond and passed rigorous thermal shock tests. A chip-scale and flip-chip capable power device was also developed. The novel package combined the ease of assembly of a discrete device with a performance exceeding a wire bonded module. It occupied a 14× smaller footprint than a discrete device, and offered power loop inductances which were less than a third of a conventional wire bonded module. A detailed manufacturing process flow and qualification is included in this dissertation. These novel devices were implemented in various electrical systems—a discrete Schottky barrier diode package, a half-bridge module with external gate drive, and finally a half-bridge with integrated gate driver in-module. The results of these investigations have been reported and their benefits assessed. The wire bondless modules showed \u3c 5% overshoot under all test conditions. No observable detrimental effects due to dv/dt were observed for any of the modules even under aggressive voltage slew rates of 20-25 V/ns