Investigating, Optimizing, and Emulating Candidate Architectures for On-Board Space Processing

With increasing computational demands in the defense and commercial industries, future space missions will require new, high-performance architectures. Extensive research, benchmarking, and analysis of candidate architectures is required before performing the expensive, time-consuming process of radiation-hardening on suitable devices. In this work, we first compare two such candidate architectures: the Texas Instruments KeyStone II octa-core DSP and the ARM Cortex-A53 quad-core CPU. We evaluate the performance of a key kernel used in space applications, the Fast Fourier Transform (FFT), and a key space application, the complex ambiguity function (CAF), on each architecture. We also develop and evaluate a direct-memory access scheme to take advantage of the KeyStone II architecture to perform FFTs. The KeyStone II’s batched 1D-FFT performance-per-watt is 4.1 times greater than the ARM Cortex-A53 and the CAF performance-per-watt is 1.8 times greater. Next, we develop and employ an emulator to study the performance of the High-Performance Spaceflight Computing (HPSC) processor. The HPSC processor is a future architecture under development by Boeing and funded by NASA and AFRL for their future space missions. HPSC is comprised of “chiplets” which have two quad-core ARM Cortex-A53 CPUs connected by an AMBA bus. These chiplets can be connected by different serial interfaces depending on mission needs. By employing two ARM platforms, an octa-core ARM architecture and two quad-core ARM architectures connected by Ethernet, we project HPSC performance for FFTs and another key space application: synthetic-aperture radar (SAR). We project that SAR will scale well on a multi-chiplet platform with a performance gain of 2.94 over a single US+ board when using two connected chiplets. Our research provides new insights on the tradeoffs encountered when parallelizing functions on these candidate architectures, including novel optimization techniques for each architectures

Comparative Benchmarking Analysis of Next-Generation Space Processors

Researchers, corporations, and government entities are seeking to deploy increasingly compute-intensive workloads on space platforms. This need is driving the development of two new radiation-hardened, multi-core space processors, the BAE Systems RAD5545(TM) processor and the Boeing High-Performance Spaceflight Computing (HPSC) processor. As these systems are in the development phase as of this writing, the Freescale P5020DS and P5040DS systems, based on the same PowerPC e5500 architecture as the RAD5545 processor, and the Hardkernel ODROID-C2, sharing the same ARM Cortex-A53 core as the HPSC processor, were selected as facsimiles for evaluation. Several OpenMP-parallelized applications, including a color search, Sobel filter, Mandelbrot set generator, hyperspectral-imaging target classifier, and image thumbnailer, were benchmarked on these processing platforms. Performance and energy consumption results on these facsimiles were scaled to forecasted frequencies of the radiationhardened devices in development. In these studies, the RAD5545 achieved the highest and most consistent parallel efficiency, up to 99%. The HPSC processor achieved lower execution times, averaging about half that of the RAD5545 processor, with lower energy consumption. The evaluated applications achieved a speedup of 3.9 times across four cores. The frequency-scaling methods were validated by comparing the set of scaled measures with data points from an underclocked facsimile, which yielded an average accuracy of 97% between estimated and measured results. These performance outcomes help to quantify the capabilities of both the RAD5545 and HPSC processors for on-board parallel processing of computationally-demanding applications for future space missions

A review of synthetic-aperture radar image formation algorithms and implementations: a computational perspective

Designing synthetic-aperture radar image formation systems can be challenging due to the numerous options of algorithms and devices that can be used. There are many SAR image formation algorithms, such as backprojection, matched-filter, polar format, Range–Doppler and chirp scaling algorithms. Each algorithm presents its own advantages and disadvantages considering efficiency and image quality; thus, we aim to introduce some of the most common SAR image formation algorithms and compare them based on these two aspects. Depending on the requisites of each individual system and implementation, there are many device options to choose from, for in stance, FPGAs, GPUs, CPUs, many-core CPUs, and microcontrollers. We present a review of the state of the art of SAR imaging systems implementations. We also compare such implementations in terms of power consumption, execution time, and image quality for the different algorithms used.info:eu-repo/semantics/publishedVersio

Design and Verification of Bus Monitor in Debug and Trace sub-system in Event Socket

This thesis introduces the concept behind the Event Socket (ES) HW and debug and trace architecture in ES, a hardware accelerator targeted for a baseband SoC. The SoC handles the baseband layer 1 processing for multi-RAT (radio access technology), both 4G (LTE) and 5GNR (new radio). The motivation behind ES boils down to the bottleneck that Amdahl’s law infers. ES is essentially used for dynamic load balancing among heterogenous set of processing engines such as processors, DSPs, microcontrollers, ASIPS and other hardware accelerators. The work done for this thesis involves the register transfer level (RTL) implementation of the bus monitor in DTSS architecture and its verification. Bus monitor unit in DTSS is non-trivial. It is responsible for capturing the transaction non-invasively on the interfaces it is connected to and produce a trace input data for ARM CoreSight architecture. Verification of a system design is critical. Pre-silicon verification of an SoC ensures that the design works as per the requirement. The verification in this work is based on UVM. The hardware description language used for the work is VHDL. DTSS architecture in ES has bus monitors to monitor the interfaces along with the standard ARM CoreSight components like System Trace Macrocell and Embedded Trace FIFO. The requirements include the features such as data capture, extraction, filtering and AXI translation for the bus monitor. These features were verified against the output from a reference model. In addition, register access was also verified. VIP from the scratch was developed for the bus monitor functional verification while for the register access, existing Nokia AXI VIP was used. The DTSS in the event socket allows non-intrusive trace of the hardware events inside the event socket thereby ensuring the correctness of the SW. In the SoC level, ES debug and trace architecture is instantiated in DTSS sub-system of the entire SoC

Computer Aided Verification

This open access two-volume set LNCS 13371 and 13372 constitutes the refereed proceedings of the 34rd International Conference on Computer Aided Verification, CAV 2022, which was held in Haifa, Israel, in August 2022. The 40 full papers presented together with 9 tool papers and 2 case studies were carefully reviewed and selected from 209 submissions. The papers were organized in the following topical sections: Part I: Invited papers; formal methods for probabilistic programs; formal methods for neural networks; software Verification and model checking; hyperproperties and security; formal methods for hardware, cyber-physical, and hybrid systems. Part II: Probabilistic techniques; automata and logic; deductive verification and decision procedures; machine learning; synthesis and concurrency. This is an open access book

National synchrotron light source. Activity report, October 1, 1995--September 30, 1996

The hard work done by the synchrotron radiation community, in collaboration with all those using large-scale central facilities during 1995, paid off in FY 1996 through the DOE`s Presidential Scientific Facilities Initiative. In comparison with the other DOE synchrotron radiation facilities, the National Synchrotron Light Source benefited least in operating budgets because it was unable to increase running time beyond 100%-nevertheless, the number of station hours was maintained. The major thrust at Brookhaven came from a 15% increase in budget which allowed the recruitment of seven staff in the beamlines support group and permitted a step increment in the funding of the extremely long list of upgrades; both to the sources and to the beamlines. During the December 1995 shutdown, the VUV Ring quadrant around U10-U12 was totally reconstructed. New front ends, enabling apertures up to 90 mrad on U10 and U12, were installed. During the year new PRTs were in formation for the infrared beamlines, encouraged by the investment the lab was able to commit from the initiative funds and by awards from the Scientific Facilities Initiative. A new PRT, specifically for small and wide angle x-ray scattering from polymers, will start work on X27C in FY 1997 and existing PRTs on X26C and X9B working on macromolecular crystallography will be joined by new members. Plans to replace aging radio frequency cavities by an improved design, originally a painfully slow six or eight year project, were brought forward so that the first pair of cavities (half of the project for the X-Ray Ring) will now be installed in FY 1997. Current upgrades to 350 mA initially and to 438 mA later in the X-Ray Ring were set aside due to lack of funds for the necessary thermally robust beryllium windows. The Scientific Facilities Initiative allowed purchase of all 34 windows in FY 1996 so that the power upgrade will be achieved in FY 1997