A 32x32 50ps Resolution 10 bit Time to Digital Converter Array in 130nm CMOS for Time Correlated Imaging

We report the design and characterisation of a 32x32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50mm pitch TDC array exhibits a minimum time resolution of 50ps, with accuracy of ±0.5 LSB DNL and 4 LSB INL. Process, voltage and temperature compensation (PVT) is achieved by locking the array to a stable external clock. The resulting time correlated pixel array is a viable candidate for single photon counting (TCSPC) applications such as fluorescent lifetime imaging microscopy (FLIM), nuclear or 3D imaging and permits scaling to larger array formats

Um amplificador de transimpedância de ganho variável para aplicação em osciladores baseados em MEMS

Orientador: José Alexandre DinizDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: Um amplificador de transimpedância (TIA) de ganho variável é apresentado. Implementado em tecnologia 0,18 'mi'm, o projeto relatado possui a finalidade de prover um amplificador de sustentação para osciladores baseados em ressonadores do tipo MEMS (Micro-Electro-Mechanical System). Entre outros, as peculiaridades de projeto envolvem um desafiante compromisso entre Ganho, Largura de Banda, Ruído e Consumo de potência. Sendo assim, o amplificador foi implementado através do cascateamento de quatro estágios de ganho similares, lançando-se mão de realimentação do tipo shunt-shunt para diminuir as impedâncias de entrada e saída. Através do emprego de um estágio de ganho variável, uma alta faixa dinâmica de ganho é alcançada (53 dB), com um ganho máximo de transimpedância de 118 dB'ômega'...Observação: O resumo, na íntegra, poderá ser visualizado no texto completo da tese digitalAbstract: A variable gain Transimpedance Amplifier (TIA) is presented. Realized in 0.18 'mi'm technology, this amplifier was conceived with the purpose of providing oscillation sustaining for Micro-Electro-Mechanical System (MEMS) based oscillators. Facing a quite challenging trade-off between Gain, Bandwidth, Noise and Power consumption, the TIA was implemented through the cascade of four similar gain stages, with the application of shunt-shunt feedback to lower both input and output resistances. With the employment of a variable-gain stage, this TIA presents a large gain tunability of 53 dB, with a also large maximum transimpedance gain of 118 dB'omega'...Note: The complete abstract is available with the full electronic documentMestradoEletrônica, Microeletrônica e OptoeletrônicaMestre em Engenharia Elétric

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

Low-pass CMOS Sigma-Delta Converter

A crescente necessidade em dar-se uma melhor saúde à população obriga ao desenvolvimento de novos e melhores dispositivos médicos. Atualmente, uma área de desenvolvimento importante é a de dispositivos portáteis para análise de sinais biológicos, tais como o eletrocardiograma ou o electroencefalograma, ajudando os profissionais de saúde a fazer rápidos diagnósticos no terreno, ou mesmo para serem usados por cidadãos que necessitem de vigilância constante. O desenvolvimento destes aparelhos traz novos desafios para a comunidade cientifica, nomeadamente na interface analógico/digital, na qualidade dos dados obtidos e no gasto energético. Para se conceber um bom dispositivos médico é necessário um conversor analógico/digital para frequências baixas, com baixo consumo energético e elevada resolução. Esta dissertação começa por fornecer ao leitor a teoria básica sobre conversores analógico/digital (ADC) e estado de arte. Como principal objetivo do trabalho desenvolvido, é descrito o desenho de um ADC baseado numa arquitetura Sigma-Delta que vá de encontro aos requisitos mencionados. O conversor foi implementado numa tecnologia 130 nm CMOS, usando uma frequência de amostragem de 1 MHz, com uma largura de banda de 1 kHz e tensão de alimentação 1,2 V. É usada, nos integradores do sigma-delta, uma invulgar tipologia de Opamp de forma a obter um ganho elevado, sem recurso a técnicas cascode. O quantizador possui uma resolução de 1,5 bits e é realizado com dois comparadores dinâmicos, de forma a minimizar o consumo energético.The growing need to provide better health for the population requires the development of new and better medical devices. Portable devices for the analysis of biological signals, such as the electrocardiogram or electroencephalogram, is nowadays an important development, helping health professionals to come up with fast diagnoses on the field, or even for use by citizens who require constant vigilance . Developing these devices brings new challenges to the scientific community, namely at the analog/digital interface, the quality of data and power consumption. In order to design a good medical device it is necessary an analog/digital converter for low frequencies, with low power consumption and high resolution. This dissertation begins by providing the reader with the basic theory of analog/digital (ADC) and its state of the art. The main goal of the work is the design of an ADC based on a Sigma-Delta architecture that meets the necessary medical requirements. The converter was implemented in a 130 nm CMOS technology using a sampling frequency of 1 MHz, with a bandwidth of 1 kHz, and a source voltage of 1.2 V. The integrators of sigma-delta employs an unusual Opamp typology in order to reach a high gain, without resourcing to cascode techniques. The quantizer has a resolution of 1.5 bits and is realized with two dynamic comparators, in order to minimize power consumption

High Speed Fully Monolihic Self-Triggered Dc-Dc Buck Converter

The integration of DC-DC converter in standard CMOS process faces challenges from the low transistor breakdown voltages, poor quality factor and large size on-chip capacitors and inductors. The standard solution to deal with the problem of MOS transistor’s low breakdown voltage is using cascode configuration in the output stage. High-side PMOS and low-side NMOS power transistors in on-chip buck converter are switched ON and OFF with non-overlapping driving signals whose duty- cycle regulate the output voltage of converter. The non-overlapping driving signals are required to avoid short-circuit losses through power transistors. By using the cascode configuration, driving signals for high-side PMOS and low-side NMOS power switching transistors operate in different voltage domains. To overcome this problem, the voltage level shifters are needed to transfer driving signals between two voltage domains. However, associated power losses and additional timing delays in conventional level shifters may deteriorate the overall efficiency of converter. In order to avoid the losses and timing delays associated with the level shifters, a self-triggered buck converter is proposed in this work. The high-side driving signal is generated from the converter output via inductive feedback. The inductive feedback eliminates the required level shifters needed for transferring the driving signal to highside power transistor. The inductive feedback has fast response and provides adaptive dead-time that avoids short circuit losses with no additional hardware. Output voltage regulation is realized by controlling the duty-cycle of the signal switching the low-side NMOS transistor. Simulations are done on Cadence 45nm CMOS General Process Design Kit(GPDK) and show that the efficiency of self-triggered converter (64.25%) is better than the efficiency of a hard-switching buck converter(63.21%), even when the level shifter losses and delays are not taken into account. The converter generate output voltage ~1.5V ± 20mV and average load current 100mA ± 3mA from 3V-3.6V input at a switching frequency of 360MHz. In order to closely match real circuit behavior, layout is made and final simulations are carried out with extracted layout and PCB Parasitics. The converter is fully integrated with 1.73×1.62[mm×mm] area on silicon including power stage, transformer, decoupling capacitors and pad

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

A spatial contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems

We present a 32 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57% to 6.6% (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is 58 m 56 m, while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35- m CMOS process.This work was supported by Spanish Research Grants TIC2003-08164-C03-01 (SAMANTA), TEC2006-11730-C03-01 (SAMANTA-II), and EU grant IST-2001-34124 (CAVIAR). JCS was supported by the I3P program of the Spanish Research Council. RSG was supported by a national grant from the Spanish Ministry of Education and Science.Peer reviewe

Designing Flexible, Energy Efficient and Secure Wireless Solutions for the Internet of Things

The Internet of Things (IoT) is an emerging concept where ubiquitous physical objects (things) consisting of sensor, transceiver, processing hardware and software are interconnected via the Internet. The information collected by individual IoT nodes is shared among other often heterogeneous devices and over the Internet. This dissertation presents flexible, energy efficient and secure wireless solutions in the IoT application domain. System design and architecture designs are discussed envisioning a near-future world where wireless communication among heterogeneous IoT devices are seamlessly enabled. Firstly, an energy-autonomous wireless communication system for ultra-small, ultra-low power IoT platforms is presented. To achieve orders of magnitude energy efficiency improvement, a comprehensive system-level framework that jointly optimizes various system parameters is developed. A new synchronization protocol and modulation schemes are specified for energy-scarce ultra-small IoT nodes. The dynamic link adaptation is proposed to guarantee the ultra-small node to always operate in the most energy efficiency mode, given an operating scenario. The outcome is a truly energy-optimized wireless communication system to enable various new applications such as implanted smart-dust devices. Secondly, a configurable Software Defined Radio (SDR) baseband processor is designed and shown to be an efficient platform on which to execute several IoT wireless standards. It is a custom SIMD execution model coupled with a scalar unit and several architectural optimizations: streaming registers, variable bitwidth, dedicated ALUs, and an optimized reduction network. Voltage scaling and clock gating are employed to further reduce the power, with a more than a 100% time margin reserved for reliable operation in the near-threshold region. Two upper bound systems are evaluated. A comprehensive power/area estimation indicates that the overhead of realizing SDR flexibility is insignificant. The benefit of baseband SDR is quantified and evaluated. To further augment the benefits of a flexible baseband solution and to address the security issue of IoT connectivity, a light-weight Galois Field (GF) processor is proposed. This processor enables both energy-efficient block coding and symmetric/asymmetric cryptography kernel processing for a wide range of GF sizes (2^m, m = 2, 3, ..., 233) and arbitrary irreducible polynomials. Program directed connections among primitive GF arithmetic units enable dynamically configured parallelism to efficiently perform either four-way SIMD GF operations, including multiplicative inverse, or a long bit-width GF product in a single cycle. This demonstrates the feasibility of a unified architecture to enable error correction coding flexibility and secure wireless communication in the low power IoT domain.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137164/1/yajchen_1.pd