433 research outputs found
A Methodology for Implementing RF BiSTs in Production Testing to Replace RF Conventional Tests
Production testing of Radio Frequency (RF) devices is challenging due to the complex nature of the tests that have to be performed to verify functionality. In this dissertation a methodology to replace the complex and expensive RF functional tests with defect-oriented Built-in Self Tests (BiSTs) is detailed. If a design has sufficient margin to RF specifications then RF tests can be replaced with structural tests using a new data analysis technique called quadrant analysis, which is presented. Data from the analysis of over one million production units of said System on Chip (SoC) is presented along with the results of the analysis. The BiST techniques that have been used are discussed and a Texas Instruments 65 nm RF SoC with a Bluetooth and a FM core was used as a case study. The defect models that were used to develop the BiSTs are discussed as well. The scenario in which a design does not have sufficient margin to specification is also discussed. The data analysis method required in such a case is a regression analysis and the data from such an analysis is shown. The results prove that it is possible to replace expensive RF conventional tests with structural tests and that modern RFCMOS process technology and advances in design like the Digital Radio Processor (DRPTM) technology enable this. The Defective Parts Per Million (DPPM) impact of making this replacement is 27 units and is acceptable for RFCMOS high volume products. Finally, data showing test cost reduction of about 38% that resulted from the elimination of RF conventional tests is presented
Characterisation and mitigation of long-term degradation effects in programmable logic
Reliability has always been an issue in silicon device engineering, but until now it has been
managed by the carefully tuned fabrication process. In the future the underlying physical
limitations of silicon-based electronics, plus the practical challenges of manufacturing with such
complexity at such a small scale, will lead to a crunch point where transistor-level reliability must
be forfeited to continue achieving better productivity.
Field-programmable gate arrays (FPGAs) are built on state-of-the-art silicon processes, but it
has been recognised for some time that their distinctive characteristics put them in a favourable
position over application-specific integrated circuits in the face of the reliability challenge. The
literature shows how a regular structure, interchangeable resources and an ability to reconfigure
can all be exploited to detect, locate, and overcome degradation and keep an FPGA application
running.
To fully exploit these characteristics, a better understanding is needed of the behavioural
changes that are seen in the resources that make up an FPGA under ageing. Modelling is an
attractive approach to this and in this thesis the causes and effects are explored of three important
degradation mechanisms. All are shown to have an adverse affect on FPGA operation, but their
characteristics show novel opportunities for ageing mitigation.
Any modelling exercise is built on assumptions and so an empirical method is developed
for investigating ageing on hardware with an accelerated-life test. Here, experiments show that
timing degradation due to negative-bias temperature instability is the dominant process in the
technology considered.
Building on simulated and experimental results, this work also demonstrates a variety of methods for increasing the lifetime of FPGA lookup tables. The pre-emptive measure of wear-levelling
is investigated in particular detail, and it is shown by experiment how di fferent reconfiguration
algorithms can result in a significant reduction to the rate of degradation
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Materials and processes for advanced lithography applications
textStep and Flash Imprint Lithography (S-FIL) is a high resolution, next-generation lithography technique that uses an ambient temperature and low pressure process to replicate high resolution images in a UV-curable liquid material. Application of the S-FIL process in conjunction with multi-level imprint templates and new imprint materials enables one S-FIL step to reproduce the same structures that require two photolithography steps, thereby greatly reducing the number of patterning steps required for the copper, dual damascene process used to fabricate interconnect wirings in modern integrated circuits. Two approaches were explored for the implementation of S-FIL in the dual damascene process: sacrificial imprint materials and imprintable dielectric materials. Sacrificial imprint materials function as a pattern recording medium during S-FIL and a three-dimensional etch mask during the dielectric substrate etch, enabling the simultaneous patterning of both the via and metal structures in the dielectric substrate. Development of sacrificial imprint materials and the associated imprint and etch processes are described. Application of S-FIL and the sacrificial imprint material in a commercial copper dual damascene process successfully produced functional copper interconnect structures, demonstrating the feasibility of integrating multi-level S-FIL in the copper dual damascene process. Imprintable dielectric materials are designed to combine the multi-level patterning capability of S-FIL with novel dielectric precursor materials, enabling the simultaneous deposition and patterning of the interlayer dielectric material. Several candidate imprintable dielectric materials were evaluated: sol-gel, polyhedral oligomeric silsesquioxane (POSS) epoxide, POSS acrylate, POSS azide, and POSS thiol. POSS thiol shows the most promise as functional imprintable dielectric material, although additional work in the POSS thiol formulation and viscous dispense process are needed to produce functional interconnect structures. Integration of S-FIL with imprintable dielectric materials would enable further streamlining of the dual damascene fabrication process. The fabrication of electronic devices on flexible substrates represents an opportunity for the development of macroelectronics such as flexible displays and large area devices. Traditional optical lithography encounters alignment and overlay limitations when applied on flexible substrates. A thermally activated, dual-tone photoresist system and its associated etch process were developed to enable the simultaneous patterning of two device layers on a flexible substrate.Chemical Engineerin
On-chip probe metrology
The semiconductor market was valued at over $270 billion in 2007, with projections to continue steady growth [7]. Any manufacturing process of this volume is tightly controlled to ensure high efficiency, and improvements are readily sought after. Despite semiconductor fabrication process advancements allowing circuits to contain larger numbers of transistors in smaller package sizes, there has not been any significant change in the way these circuits interface with test systems before packaging. This limitation causes the area overhead occupied by circuit contacts, known as bond pads, to become increasingly costly. To amend the situation, VLSI designers have attempted to reduce bond pads size and pitch as much as possible while retaining reliable probing accuracy [15]. Currently, there is no standard solution to assess the accuracy of probe stations inline with wafer testing. As such, a balance must be struck between overhead cost of large bond pads and operational cost spent analyzing probe performance off-line. A feedback loop on probe card performance during wafer fabrication sort could allow plants to recalibrate probe cards before a yield drop is detected, thus improving yield and saving operational costs [26]. This thesis demonstrates a proof of concept design that offers a viable solution to perform probe metrology in-line with wafer-level circuit testing. A versatile circuit was designed and laid out that promises fine accuracy resolution of 3.21 μm, and fast test time of 1.25 ms per probe
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Investigation into the wafer-scale integration of fine-grain parallel processing computer systems
This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.This thesis investigates the potential of wafer-scale integration (WSI) for the implementation of low-cost fine-grain parallel processing computer systems. As WSI is a relatively new subject, there was little work on which to base investigations. Indeed, most WSI architectures existed only as untried and sometimes vague proposals. Accordingly, the research strategy approached this problem by identifying a representative WSI structure and architecture on which to base investigations. An analysis of architectural proposals identified associative memory to be general purpose parallel processing component used in a wide range of WSI architectures. Furthermore, this analysis provided a set of WSI-level design requirements to evaluate the sustainability of different architectures as research vehicles. The WSI-ASP (WASP) device, which has a large associative memory as its main component is shown to meet these requirements and hence was chosen as the research vehicle. Consequently, this thesis addresses WSI potential through an in-depth investigation into the feasibility of implementing a large associative memory for the WASP device that meets the demanding technological constraints of WSI. Overall, the thesis concludes that WSI offers significant potential for the implementation of low-cost fine-grain parallel processing computer systems. However, due to the dual constraints of thermal management and the area required for the power distribution network, power density is a major design constraint in WSI. Indeed, it is shown that WSI power densities need to be an order of magnitude lower than VLSI power densities. The thesis demonstrates that for associative memories at least, VLSI designs are unsuited to implementation in WSI. Rather, it is shown that WSI circuits must be closely matched to the operational environment to assure suitable power densities. These circuits are significantly larger than their VLSI equivalents. Nonetheless, the thesis demonstrates that by concentrating on the most power intensive circuits, it is possible to achieve acceptable power densities with only a modest increase in area overheads.SER
OXIDATION OF SILICON - THE VLSI GATE DIELECTRIC
Silicon dominates the semiconductor industry for good reasons. One factor is the stable, easily formed, insulating oxide, which aids high performance and allows practical processing. How well can these virtues survive as new demands are made on integrity, on smallness of feature sizes and other dimensions, and on constraints on processing and manufacturing methods? These demands make it critical to identify, quantify and predict the key controlling growth and defect processes on an atomic scale.The combination of theory and novel experiments (isotope methods, electronic noise, spin resonance, pulsed laser atom probes and other desorption methods, and especially scanning tunnelling or atomic force microscopies) provide tools whose impact on models is just being appreciated. We discuss the current unified model for silicon oxidation, which goes beyond the traditional descriptions of kinetic and ellipsometric data by explicitly addressing the issues raised in isotope experiments. The framework is still the Deal-Grove model, which provides a phenomenology to describe the major regimes of behaviour, and gives a base from which the substantial deviations can be characterized. In this model, growth is limited by diffusion and interfacial reactions operating in series. The deviations from Deal-Grove are most significant for just those first tens of atomic layers of oxide which are critical for the ultra-thin oxide layers now demanded. Several features emerge as important. First is the role of stress and stress relaxation. Second is the nature of the oxide closest to the Si, both its defects and its differences from the amorphous stoichiometric oxide further out, whether in composition, in network topology, or otherwise. Thirdly, we must consider the charge states of both fixed and mobile species. In thin films with very different dielectric constants, image terms can be important; these terms affect interpretation of spectroscopies, the injection of oxidant species and relative defect stabilities. This has added importance now that P-b concentrations have been correlated with interfacial stress. This raises further issues about the perfection of the oxide random network and the incorporation of interstitial species like molecular oxygen.Finally, the roles of contamination, particles, metals, hydrocarbons etc are important, as is interface roughness. These features depend on pre-gate oxide cleaning and define the Si surface that is to be oxidized which may have an influence on the features listed above
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