Programmed state assignment algorithms for asynchronous sequential machines.

An important step in the synthesis procedure for realizing a normal fundamental mode asynchronous sequential circuit is the internal state assignment. Although systematic methods have been developed to construct minimum-transition-time state assignments, they become long and tedious with hand methods for machines with more than 7 or 8 internal states. To extend the application of these algorithms to larger problems, this paper presents an efficient digital computer program for generating minimum-variable state assignments. An alternate program is also presented which, though shorter, does not guarantee a minimum-variable assignment --Abstract, page ii

Synthesis heuristics for large asynchronous sequential circuits

Many well-known synthesis procedures for asynchronous sequential circuits produce minimal or near-minimal results, but are practical only for very small problems. These algorithms become unwieldy when applied to large circuits with, for example, three or more input variables and twenty or more internal states. New heuristic procedures are described which permit the synthesis of very large machines. Although the resulting designs are generally not minimal, the heuristics are able to produce near-minimal solutions orders of magnitude more rapidly than the minimal algorithms. A method for specifying sequential circuit behavior is presented. Input-output sequences define submachines or modules. When properly interconnected, these modules form the required sequential circuit. It is shown that the waveform and interconnection specifications may easily be translated into flow table form. A large flow table simplification heuristic is developed. The algorithm may be applied to tables having hundreds of rows, and handles both normal and non-normal mode circuit specifications. Nonstandard state assignment procedures for normal, fundamental mode asynchronous sequential circuits are examined. An algorithm for rapidly generating large flow table internal state assignments is proposed. The algorithms described have been programmed in PL/1 and incorporated into an automated design system for asynchronous circuits; the system also includes minimum and near-minimum variable state assignment generators, a code evaluation routine, a design equation generator, and two Boolean equation simplification procedures. Large sequential circuits designed using the system illustrate the utility of the heuristic procedures --Abstract, pages ii-iii

Automation In The Design Of Asynchronous Sequential Circuits

Sequential switching circuits are commonly classified as being either synchronous or asynchronous. Clock pulses synchronize the operations of the synchronous circuit. The operation of an asynchronous circuit is usually assumed to be independent of such clocks. The operating speed of an asynchronous circuit is thus limited only by basic device speed. One disadvantage of asynchronous circuit design has been the complexity of the synthesis procedures for large circuits

Next-state equation generation for asynchronous sequential circuits - normal mode

This paper describes the known methods of generating next-state equations for asynchronous sequential circuits operating in normal fundamental mode. First, the methods that have been previously developed by other authors are explained and correlated in a simple and uniform language in order that the subtle differences of these approaches can be seen. This review is then followed by a development of a new method for generating minimal next-state equations which has some advantages over the previous methods. From the comparison of the previous known methods, it is noted that any one of these methods may be desirable for certain designs since each has some advantages that the others do not have. However, these methods also have limitations in that some methods can only be used with particular types of assignments. Also, as flow tables become larger the amount of work required to use some of these methods becomes excessive and tedious. The method developed here is a simple and straightforward approach which can be used for any unicode, single transition time assignment and will easily lend itself to computer application. The heart of this method emanates from the role that the Karnaugh map plays in the conventional approach for generating the next-state equations. The main advantage of this method seems to be its capability and proficiency in handling large flow tables --Abstract, pages ii-iii

Implications of Tracey's theorem to asynchronous sequential circuit design

Tracey's Theorem has long been recognized as essential in generating state assignments for asynchronous sequential circuits. This paper shows that Tracey's Theorem also has a significant impact in generating the design equations. Moreover, this theorem is important to the fundamental understanding of asynchronous sequential operation. The results of this work simplify asynchronous logic design. Moreover, detection of safe circuits is made easier

State Assignment Selection In Asynchronous Sequential Circuits

Methods already exist for the construction of critical race-free assignments for asynchronous sequential circuits. Some of these methods permit the construction of many assignments for the same flow table. The algorithm presented here consists of two easy to apply tests which select that critical race-free assignment most likely to produce a set of simple next-state equations. The algorithm has been programmed. Copyright © 1970 by The Institute of Electrical and Electronics Engineers, Inc

A method for generating UTS assignments with an iterative state transition algorithm

There is a lack of systematic procedures that can be used to find uni-code totally sequential (UTS) assignments from a flow table description of an asynchronous sequential circuit. Presented here is an iterative internal state assignment method. This method consists of three algorithms. The first generates a minimum variable initial assignment from a flow table description. The second tests the validity of this assignment by constructing minimum length transition paths without crossover and the third augments this assignment by adding an internal state variable in the event that all transition paths cannot be constructed without crossover. The second and the third algorithms are used iteratively until a valid non-universal UTS assignment is produced. The iterative state assignment method is systematic in all its phases. Every phase of the method includes more than one algorithm to perform the same function. The algorithm producing minimum length transition paths is very powerful in that it can also be used in conjunction with other state assignment methods producing either universal or non-universal UTS assignments. After one obtains a valid UTS assignment an algorithm is provided to replace some or all of the totally sequential transitions with mixed mode transitions. This reduces the number of subtransitions in a given transition path and therefore speeds up the transition time considerably --Abstract, page ii

Synthesis of multiple-input change asynchronous finite state machines

Asynchronous finite state machines (AFSMS) have been limited because multiple-input changes have been disallowed. In this paper, we present an architecture and synthesis system to overcome this limitation. The AFSM marks potentially hazardous state transitions, and prevents output during them. A synthesis tool to create the AFS M incorporates novel algorithms to detect the hazardous states

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed