RF Circuit linearity optimization using a general weak nonlinearity model

This paper focuses on optimizing the linearity in known RF circuits, by exploring the circuit design space that is usually available in today’s deep submicron CMOS technologies. Instead of using brute force numerical optimizers we apply a generalized weak nonlinearity model that only involves AC transfer functions to derive simple equations for obtaining design insights. The generalized weak nonlinearity model is applied to three known RF circuits: a cascode common source amplifier, a common gate LNA and a CMOS attenuator. It is shown that in deep submicron CMOS technologies the cascode transistor in both the common source amplifier and in the common gate amplifier significantly contributes IM3 distortion. Some design insights are presented for reducing the cascode transistor related distortion, among which moderate inversion biasing that improves IIP3 by 10 dB up to 5 GHz in a 90 nm CMOS process. For the attenuator, a wideband IM3 cancellation technique is introduced and demonstrated using simulations

Millimeter-Wave Concurrent Dual-Band Sige Bicmos Rfic Phased-Array Transmitter and Components

A concurrent dual-band phased-array transmitter (TX) and its constituent components are studied in this dissertation. The TX and components are designed for the unlicensed bands, 22–29 and 57–64 GHz, using a 0.18-μm BiCMOS technology. Various studies have been done to design the components, which are suitable for the concurrent dual-band phased-array TX. The designed and developed components in this study are an attenuator, switch, phase shifter, power amplifier and power divider. Attenuators play a key role in tailoring main beam and side-lobe patterns in a phased-array TX. To perform the function in the concurrent dual-band phased-array TX, a 22–29 and 57–64 GHz concurrent dual-band attenuator with low phase variations is designed. Signal detection paths are employed at the output of the phased-array TX to monitor the phase and amplitude deviations/errors, which are larger in the high-frequency design. The detected information enables the TX to have an accurate beam tailoring and steering. A 10–67 GHz wide-band attenuator, covering the dual bands, is designed to manipulate the amplitude of the detected signal. New design techniques for an attenuator with a wide attenuation range and improved flatness are proposed. Also, a topology of dual-function circuit, attenuation and switching, is proposed. The switching turns on and off the detection path to minimize the leakages while the path is not used. Switches are used to minimize the number of components in the phased-array transceiver. With the switches, some of the bi-directional components in the transceiver such as an attenuator, phase shifter, filter, and antenna can be shared by the TX and receiver (RX) parts. In this dissertation, a high-isolation switch with a band-pass filtering response is proposed. The band-pass filtering response suppresses the undesired harmonics and intermodulation products of the TX. Phase shifters are used in phased-array TXs to steer the direction of the beam. A 24-GHz phase shifter with low insertion loss variation is designed using a transistor-body-floating technique for our phased-array TX. The low insertion loss variation minimizes the interference in the amplitude control operation (by attenuator or variable gain amplifier) in phased-array systems. BJTs in a BiCMOS process are characterized across dc to 67 GHz. A novel characterization technique, using on-wafer calibration and EM-based de-embedding both, is proposed and its accuracy at high frequencies is verified. The characterized BJT is used in designing the amplifiers in the phased-array TX. A concurrent dual-band power amplifier (PA) centered at 24 and 60 GHz is proposed and designed for the dual-band phased-array TX. Since the PA is operating in the dual frequency bands simultaneously, significant linearity issues occur. To resolve the problems, a study to find significant intermodulation (IM) products, which increase the third intermodulation (IM3) products most, has been done. Also, an advanced simulation and measurement methodology using three fundamental tones is proposed. An 8-way power divider with dual-band frequency response of 22–29 and 57–64 GHz is designed as a constituent component of the phased-array TX

Adaptive Suppression of Interfering Signals in Communication Systems

The growth in the number of wireless devices and applications underscores the need for characterizing and mitigating interference induced problems such as distortion and blocking. A typical interference scenario involves the detection of a small amplitude signal of interest (SOI) in the presence of a large amplitude interfering signal; it is desirable to attenuate the interfering signal while preserving the integrity of SOI and an appropriate dynamic range. If the frequency of the interfering signal varies or is unknown, an adaptive notch function must be applied in order to maintain adequate attenuation. This work explores the performance space of a phase cancellation technique used in implementing the desired notch function for communication systems in the 1-3 GHz frequency range. A system level model constructed with MATLAB and related simulation results assist in building the theoretical foundation for setting performance bounds on the implemented solution and deriving hardware specifications for the RF notch subsystem devices. Simulations and measurements are presented for a Low Noise Amplifer (LNA), voltage variable attenuators, bandpass filters and phase shifters. Ultimately, full system tests provide a measure of merit for this work as well as invaluable lessons learned. The emphasis of this project is the on-wafer LNA measurements, dependence of IC system performance on mismatches and overall system performance tests. Where possible, predictions are plotted alongside measured data. The reasonable match between the two validates system and component models and more than compensates for the painstaking modeling efforts. Most importantly, using the signal to interferer ratio (SIR) as a figure of merit, experimental results demonstrate up to 58 dB of SIR improvement. This number represents a remarkable advancement in interference rejection at RF or microwave frequencies

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

Adaptive multibeam phased array design for a Spacelab experiment

The parametric tradeoff analyses and design for an Adaptive Multibeam Phased Array (AMPA) for a Spacelab experiment are described. This AMPA Experiment System was designed with particular emphasis to maximize channel capacity and minimize implementation and cost impacts for future austere maritime and aeronautical users, operating with a low gain hemispherical coverage antenna element, low effective radiated power, and low antenna gain-to-system noise temperature ratio

SOI RF-MEMS Based Variable Attenuator for Millimeter-Wave Applications

The most-attractive feature of microelectromechanical systems (MEMS) technology is that it enables the integration of a whole system on a single chip, leading to positive effects on the performance, reliability and cost. MEMS has made it possible to design IC-compatible radio frequency (RF) devices for wireless and satellite communication systems. Recently, with the advent of 5G, there is a huge market pull towards millimeter-wave devices. Variable attenuators are widely employed for adjusting signal levels in high frequency equipment. RF circuits such as automatic gain control amplifiers, broadband vector modulators, full duplex wireless systems, and radar systems are some of the primary applications of variable attenuators. This thesis describes the development of a millimeter-wave RF MEMS-based variable attenuator implemented by monolithically integrating Coplanar Waveguide (CPW) based hybrid couplers with lateral MEMS varactors on a Silicon–on–Insulator (SOI) substrate. The MEMS varactor features a Chevron type electrothermal actuator that controls the lateral movement of a thick plate, allowing precise change in the capacitive loading on a CPW line leading to a change in isolation between input and output. Electrothermal actuators have been employed in the design instead of electrostatic ones because they can generate relatively larger in-line deflection and force within a small footprint. They also provide the advantage of easy integration with other electrical micro-systems on the same chip, since their fabrication process is compatible with general IC fabrication processes. The development of an efficient and reliable actuator has played an important role in the performance of the proposed design of MEMS variable attenuator. A Thermoreflectance (TR) imaging system is used to acquire the surface temperature profiles of the electrothermal actuator employed in the design, so as to study the temperature distribution, displacement and failure analysis of the Chevron actuator. The 60 GHz variable attenuator was developed using a custom fabrication process on an SOI substrate with a device footprint of 3.8 mm x 3.1 mm. The fabrication process has a high yield due to the high-aspect-ratio single-crystal-silicon structures, which are free from warping, pre-deformation and sticking during the wet etching process. The SOI wafer used has a high resistivity (HR) silicon (Si) handle layer that provides an excellent substrate material for RF communication devices at microwave and millimeter wave frequencies. This low-cost fabrication process provides the flexibility to extend this module and implement more complex RF signal conditioning functions. It is thus an appealing candidate for realizing a wide range of reconfigurable RF devices. The measured RF performance of the 60 GHz variable attenuator shows that the device exhibits attenuation levels (|S21|) ranging from 10 dB to 25 dB over a bandwidth of 4 GHz and a return loss of better than 20 dB. The thesis also presents the design and implementation of a MEMS-based impedance tuner on a Silicon-On-Insulator (SOI) substrate. The tuner is comprised of four varactors monolithically integrated with CPW lines. Chevron actuators control the lateral motion of capacitive thick plates used as contactless lateral MEMS varactors, achieving a capacitance range of 0.19 pF to 0.8 pF. The improvement of the Smith chart coverage is achieved by proper choice of the electrical lengths of the CPW lines and precise control of the lateral motion of the capacitive plates. The measured results demonstrate good impedance matching coverage, with an insertion loss of 2.9 dB. The devices presented in this thesis provide repeatable and reliable operation due to their robust, thick-silicon structures. Therefore, they exhibit relatively low residual stress and are free from stiction and micro-welding problems

SiGe/CMOS Millimeter-Wave Integrated Circuits and Wafer-Scale Packaging for Phased Array Systems.

Phased array systems have been used to achieve electronic beam control and fast beam scanning. In the RF-phase shifting architecture, T/R modules are required for each antenna element, and have been traditionally developed using GaAs or InP technology. This thesis demonstrates that Ka-band (35 GHz) T/R modules can also be developed using the SiGe BiCMOS technology. The designed circuit blocks include a low noise amplifier, a 4-bit phase shifter, a variable gain amplifier/attenuator, and SPDT switches. The Ka-band phase shifters are designed based on CMOS switch and miniature low-pass networks for a single-ended and differential applications, and result in 3-degree rms phase error at 35 GHz. The SiGe LNA results in a peak gain of 24 dB and a noise figure of 2.9-3.1 dB with 11 mW power consumption. The CMOS variablestep attenuator has 12-dB attenuation range (1 dB step) with very low loss and phase imbalance at 10-50 GHz. A variable gain LNA is also demonstrated at 30-40 GHz for the differential phased array receiver, and has 20-dB gain and <1-degree rms phase imbalance between the 8 different gain states and 10 dB gain control. All of these circuits show state-of-the-art performance, and the phase shifter, distributed attenuator and VGA are also first-time demonstrations at Ka-band frequencies. These circuit blocks were used in a miniature SiGe/CMOS Ka-band T/R module with a dimension of 0.93x1.33mm2, and a measured performance of 19 dB receive gain, 4-5 dB NF, 9 dB transmit gain and +5.5 dBm output P1dB. The T/R module also has 4-bit phase control and 10 dB gain control in both the transmit and receive modes. To our knowledge, this is the first demonstration of a Ka-band SiGe/CMOS T/R module to-date. Finally, a DC-110 GHz Si wafer-scale packaging technique has been developed using thermo-compression bonding and is suitable for Ka-band and even W-band T/R modules. The package transition has an insertion loss of 0.1-0.26 dB at 30-110 GHz, and the package resonances and leakage were drastically reduced by grounding the sealing ring. This is the first demonstration of a wideband resonance-free (DC-110 GHz) package using silicon technology.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/58380/1/bmin_1.pd

An X-Band power amplifier design for on-chip RADAR applications

Tremendous growth of RAdio Detecting And Ranging (RADAR) and communication electronics require low manufacturing cost, excellent performance, minimum area and highly integrated solutions for transmitter/receiver (T/R) modules, which are one of the most important blocks of RADAR systems. New circuit topologies and process technologies are investigated to fulfill these requirements of next generation RADAR systems. With the recent improvements, Silicon-Germanium Bipolar CMOS technology became a good candidate for recently used III-V technologies, such as GaAs, InP, and GaN, to meet high speed and performance requirements of present RADAR applications. As new process technologies are used, new solutions and circuit architectures have to be provided while taking into account the advantages and disadvantageous of used technologies. In this thesis, a new T/R module system architecture is presented for single/onchip X-Band phased array RADAR applications. On-chip T/R module consists of five blocks; T/R switch, single-pole double-throw (SPDT) switch, low noise amplifier (LNA), power amplifier (PA), and phase shifter. As the main focus of this thesis, a two-stage power amplifier is realized, discussed and measured. Designed in IHP's 0.25 [micrometer] SiGe BiCMOS process technology, the power amplifier operates in Class-A mode to achieve high linearity and presents a measured small-signal gain of 25 dB at 10 GHz. While achieving an output power of 22 dBm, the power amplifier has drain efficiency of 30 % in saturation. The total die area is 1 [square millimeters], including RF and DC pads. To our knowledge, these results are comparable to and/or better than those reported in the literature