Peripheral soldering of flip chip joints on passive RFID tags

Flip chip is the main component of a RFID tag. It is used in billions each year in electronic packaging industries because of its small size, high performance and reliability as well as low cost. They are used in microprocessors, cell phones, watches and automobiles. RFID tags are applied to or incorporated into a product, animal, or person for identification and tracking using radio waves. Some tags can be read from several meters away or even beyond the line of sight of the reader. Passive RFID tags are the most common type in use that employ external power source to transmit signals. Joining chips by laser beam welding have wide advantages over other methods of joining, but they are seen limited to transparent substrates. However, connecting solder bumps with anisotropic conductive adhesives (ACA) produces majority of the joints. A high percentage of them fail in couple of months, particularly when exposed to vibration. In the present work, failure of RFID tags under dynamic loading or vibration was studied; as it was identified as one of the key issue to explore. Earlier investigators focused more on joining chip to the bump, but less on its assembly, i.e., attaching to the substrate. Either of the joints, between chip and bump or between antenna and bump can fail. However, the latter is more vulnerable to failure. Antenna is attached to substrate, relatively fixed when subjected to oscillation. It is the flip chip not the antenna moves during vibration. So, the joint with antenna suffers higher stresses. In addition to this, the strength of the bonding agent i.e., ACA also much smaller compared to the metallic bond at the other end of the bump. Natural frequency of RFID tags was calculated both analytically and numerically, found to be in kilohertz range, high enough to cause resonance. Experimental investigations were also carried out to determine the same. However, the test results for frequency were seen to be in hundred hertz range, common to some applications. It was recognized that the adhesive material, commonly used for joining chips, was primarily accountable for their failures. Since components to which the RFID tags are attached to experience low frequency vibration, chip joints fail as they face resonance during oscillation. Adhesives having much lower modulus than metals are used for attaching bumps to the substrate antennas, and thus mostly responsible for this reduction in natural frequency. Poor adhesive bonding strength at the interface and possible rise in temperature were attributed to failures under vibration. In order to overcome the early failure of RFID tag joints, Peripheral Soldering, an alternative chip joining method was devised. Peripheral Soldering would replace the traditional adhesive joining by bonding the peripheral surface of the bump to the substrate antenna. Instead of joining solder bump directly to the antenna, holes are to be drilled through antenna and substrate. S-bond material, a less familiar but more compatible with aluminum and copper, would be poured in liquid form through the holes on the chip pad. However, substrates compatible to high temperature are to be used; otherwise temperature control would be necessary to avoid damage to substrate. This S-bond would form metallic joints between chip and antenna. Having higher strength and better adhesion property, S-bond material provides better bonding capability. The strength of a chip joined by Peripheral Soldering was determined by analytical, numerical and experimental studies. Strength results were then compared to those of ACA. For a pad size of 60 micron on a 0.5 mm square chip, the new chip joints with Sbond provide an average strength of 0.233N analytically. Numerical results using finite element analysis in ANSYS 11.0 were about 1% less than the closed form solutions. Whereas, ACA connected joints show the maximum strength of 0.113N analytically and 0.1N numerically. Both the estimates indicate Peripheral Soldering is more than twice stronger than adhesive joints. Experimental investigation was carried out to find the strength attained with S-bond by joining similar surfaces as those of chip pad and antenna, but in larger scale due to limitation in facilities. Results obtained were moderated to incorporate the effect of size. Findings authenticate earlier predictions of superior strengths with S-bond. A comparison with ACA strength, extracted from previous investigations, further indicates that S-bond joints are more than 10 times stronger. Having higher bonding strength than in ACA joints, Peripheral Soldering would provide better reliability of the chip connections, i.e., RFID tags. The benefits attained would pay off complexities involved in tweaking

Mechanics of Non Planar Interfaces in Flip-Chip Interconnects

With the continued proliferation of low cost, portable consumer electronic products with greater functionality, there is increasing demand for electronic packaging that is smaller, lighter and less expensive. Flip chip is an essential enabling technology for these products. The electrical connection between the chip I/O and substrate is achieved using conductive materials, such as solder, conductive epoxy, metallurgy bump (e.g., gold) and anisotropic conductive adhesives. The interconnect regions of flip-chip packages consists of highly dissimilar materials to meet their functional requirements. The mismatches in properties, contact morphology and crystal orientation at those material interfaces make them vulnerable to failure through delamination and crack growth under various loading patterns. This study encompasses contact between deformable bodies, bonding at the asperities and fracture properties at interfaces formed by the interconnects of flip-chip packages. This is achieved through experimentation and modeling at different length scales, to be able to capture the detailed microstructural features and contact mechanics at interfaces typically found in electronic systems

Experimental and modelling studies of electronic packaging interconnections formed with lead-free materials

Both the experimental and the modelling techniques have been investigated and used to investigate factors that influence the formation, quality and reliability of electronic packaging interconnections formed using solder alloys and anisotropic conductive films (ACFs). The wetting behaviours of new lead-free solders (i.e. Sn-2.8Ag-0.5Cu-1.0Bi and Sn-0.7Cu-0.3Ni) have been evaluated using the wetting balance test. This assessment ahs been performed for three soldering temperatures with three different types of fluxes. The results have been compared with the conventional Sn-Pb, Sn-Ag-Cu and Sn-Cu solders. It has been found that the wettability of the lead-free solders is not as good as that of the Sn-Pb solder. The additions of Bi into the Sn-Ag-Cu solder and Ni into the Sn-Cu solder improve the wettability that is strongly dependent on the type of the flux and the soldering temperature. In general, NC-flux is suitable for Cu-substrate whereas Ws-flux is suitable for Ni substrate, but for the Sn-2.8Ag-0.5-Cu solder on Ni substrate, good wettability has been observed with both the NC and the R-type fluxes. Computational modelling of this test has revealed that the increase in the depth and the radius of the solder bath has little effect on the wetting force, but the meniscus height decreases when the bath radius exceeds 14 mm. Dissolution of solid metals into liquid solders has been investigated through experiments and computer modelling. Microstructural studies have been carried out and the growth behaviours of the intermetallic compounds (IMCs) during wetting, solidification and isothermal ageing have been investigated. It has been found that the addition of Bi into the Sn-Ag-Cu solder reduces the consumptions of the substrates and suppresses the growth of IMCs during wetting and ageing. Similarly, the addition of Ni into the Sn-Cu solder reduces both the consumptions of the substrates and the growth of IMCs during wetting and short term ageing but enhances the growth of IMCs during long term ageing. Experimental and computer modelling techniques have been used to measure the temperature in the ACF during bonding. The temperature in an ACF joint becomes very close to the required maximum bonding temperature within the first 1 s of bonding time. The impact of this temperature on the cure process and on the ACF physical properties such as loss modulus, storage modulus, and glass transition temperature has been investigated. It has been found that the higher the bonding temperature the more the curing degree of ACF is. Rapid changes occur in the physical properties of ACF at temperatures above the glass transition point. When the ACF is cured for a long time at a high temperature, the physical properties may degrade. The adhesion strength of ACF joint increases as the curing degree increases. However, when the ACF joint undergoes a thermal aging treatment, the adhesion strength increases for the samples bonded at lower temperatures, but decreases for the samples bonded at higher temperatures. The rate of increase in the contact resistance is dramatically higher for the samples bonded at lower temperatures than for those bonded at higher temperatures. Computer modelling of the isothermal ageing of ACF joint confirms that the thermal load causes the expansion of the adhesive matrix and generates high stresses on the conductive particle. This may result in the permanent damage of the outermost conductive metallic layers as well as electrical failure. The effect of external bending loads on the electrical reliability of ACF-based interconnection has also been studied through computer modelling. The analysis reveals that ACF thickness increases at the corners of the chip-ACF joint more than that of the middle position. This causes a gap between the chip and the substrate results in the failure of the electrical interconnections

Material Selection for Interfacial Bond Layer in Electronic Packaging

In electronic packaging, typically two or more thin dissimilar plates or layers are bonded together by an extremely thin adhesive bond layer. Electronic assemblies are usually operated under high power conditions which predictably produces a high temperature environment in the electronic devices. Therefore, thermal mismatch shear and peeling stress inevitably arise at the interfaces of the bonded dissimilar materials due to differences in Coefficient of Thermal Expansion (CTE) typically during the high temperature change in the bond process. As a result, delamination failure may occur during manufacturing, machining, and field use. As such, these thermo-mechanical stresses play a very significant role in the design and reliability of the electronic packaging assembly. Consequently, critical investigations of interfacial stresses under variable load conditions in composite structure can result in a better design of electronic packaging with higher reliability and minimize or eliminate the risk of functional failure. In order to formulize bond material selection, analytical studies are carried out in order to study the influence of bond layer parameters on interfacial thermal stresses of a given package. These parameters include Coefficient of thermal expansion (CTE), poison's ratio, temperature, thickness, and stiffness (compliant and stiff) of the bond layer. From the study, stiffness and bond layer thickness are identified as the key parameters influencing interfacial shearing and peeling stresses. The other parameters namely CTE, poisons ratio has shown insignificant influence on interfacial stresses due to the very thin section of bond layer compared to the top and bottom layers. The results also show that the interfacial stresses increases proportionally with the increase of temperature in the layers. Therefore, it is very important that the temperature is maintained as low as possible during the chip manufacturing and operating stages. Since only two parameters namely stiffness and bond layer thickness are identified as the key parameters, the interface thermal mismatch stresses can be reduced or eliminated by controlling these two parameters only. Therefore the identification of suitable bond layer parameters selection with reasonable accuracy is possible even without performing optimization process. Finally, this paper proposes a Metal Matrix Composite (MMC) bond material selection approach using rule of mixture material design. The outcome of this research can be seen in the forms of practical and beneficial tools for interfacial stress evaluation and physical design and fabrication of layered assemblies. The Engineers can utilize this research outcome in conjunction with guidelines for electronic packaging under variable thermal properties of layered composites

Bond Layer Properties and Geometry Effect on Interfacial Thermo-mechanical Stresses in Bi-material Electronic Packaging Assembly

Thermo-mechanical mismatch stress is one of the reasons for mechanical as well as functional failure between two or more connected devices. In electronic packaging, two or more plates or layers are bonded together by an extremely thin layer. This thin bonding layer works as an interfacial stress compliance which is expected to alleviate the interfacial stresses between the layers. Therefore, it is very important to identify the suitable interfacial bonding characteristics for reducing the interfacial thermal mismatch stresses to maintain the structural integrity. This research work examines the influences of bond layer properties and geometry on the interfacial shearing and peeling stresses in a bi-material assembly. In this study a closed form model of bi-layered assembly is used with the up-to-date bond layer shear stress compliance expression. The key bond layer properties namely Young's modulus, coefficient of thermal expansion, Poisson's ratio, and physical parameters like temperature and thickness are considered for interfacial stress evaluation. It is observed that the Young's modulus, the thickness and the temperature of the bond layer have significant influence on the interfacial shearing and peeling stress. The results obtained are likely to be useful in designing bond layer properties in microelectronics and photonics applications

Evaluation of Anisotropic Conductive Films Based on Vertical Fibers for Post-CMOS Wafer-Level Packaging

In this paper, we investigate the mechanical and electrical properties of an anisotropic conductive film (ACF) on the basis of high-density vertical fibers for a wafer-level packaging (WLP) application. As part of the WaferBoard, a\ud reconfigurable circuit platform for rapid system prototyping,\ud ACF is used as an intermediate film providing compliant and\ud vertical electrical connection between chip contacts and a top surface of an active wafer-size large-area IC. The chosen ACF is first tested by an indentation technique. The results show that the elastic–plastic deformation mode as well as the Young’s modulus and the hardness depend on the indentation depth. Second, the efficiency of the electrical contact is tested using a uniaxial compression on a stack comprising a dummy ball grid array (BGA) board, an ACF, and a thin Al film. For three bump diameters, as the compression increases, the resistance values decrease before reaching low and stable values. Despite the BGA solder bumps exhibit plastic deformation after compression, no damage is found on the ACF film. These results show that vertical fiber ACFs can be used for nonpermanent bonding in a WLP application

Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

Development and Evaluation of Accelerated Environmental Test Methods for Products with High Reliability Requirements

Reliability testing of electronics is performed to ensure that products function as planned in specific conditions for a specified amount of time. This is usually both time-consuming and expensive and therefore test time acceleration is often required. The acceleration may be realized by using more severe stress levels or higher use cycle frequencies, but at the same time the risk increases of inducing failure mechanisms not relevant to the use conditions. As a consequence, the accelerated reliability testing of products with markedly long lifetimes and high reliability is frequently challenging. In this thesis different methods for test time acceleration for products with high reliability requirements and long service lives were studied. Both standard tests and modifications of these were used. The effect of the accelerated tests used on the failure modes and mechanisms observed was examined and the limitations of the test methods discussed. The research in this work was conducted at both interconnection level and at device level. The interconnection level testing focused on anisotropically conductive adhesive (ACA) flex-on-board (FOB) attachments. In addition to the effect of the curing process on the mechanical strength of ACA FOB attachments, their applicability and long-term performance in industrial applications was studied. According to the real-time resistance measurement the assembly tested was observed to be extremely resilient in thermal cycling and hygrothermal aging. However, a significant decrease in the mechanical strength of the FOB attachment was also seen. Hydrolysis and embrittlement of the flex material was also observed to limit the applicability of harsher hygrothermal aging conditions. Clear ACA joint failures were only observed with moisture condensation testing, but this may not be a suitable test method for applications that are not susceptible to such a stressor. The device level testing comprised reliability analysis of two frequency converter models. The older generation device and its field failure data were used as the starting point in the development of a test method that could be used to minimize testing time and to induce comparable failure modes to those occurring in the use conditions of the devices. The tests showed that only with the simultaneous use of stresses could a significant reduction in the testing time be achieved. However, the application of the same test method to the newer generation device proved challenging because of differences in materials, components and layouts. Although similar failure modes were observed in both devices, the combined effect of the stresses used on the failure mechanisms requires further study. In addition, knowledge of the service conditions, the environmental stresses and their severity is critical. The main disadvantage of simultaneous stress testing was observed to be the interpretation of the test results, especially due to the complexity of the devices tested. Moreover, the results obtained may be highly application specific. However, regardless of the difficulties in the lifetime estimation, the use of combined stresses was observed to be a practical method to study the weaknesses in a product

Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect

Semiconductor chip packaging has evolved from single chip packaging to 3D heterogeneous system integration using multichip stacking in a single module. One of the key challenges in 3D integration is the high density interconnects that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip interconnects. Anisotropic Conductive Film (ACF) technology is one of the low-temperature, fine-pitch interconnect method, which has been considered as a potential replacement for solder interconnects in line with continuous scaling of the interconnects in the IC industry. However, the conventional ACF materials are facing challenges to accommodate the reduced pad and pitch size due to the micro-size particles and the particle agglomeration issue. A new interconnect material - Nanowire Anisotropic Conductive Film (NW-ACF), composed of high density copper nanowires of ~ 200 nm diameter and 10-30 µm length that are vertically distributed in a polymeric template, is developed in this work to tackle the constrains of the conventional ACFs and serves as an inter-chip interconnect solution for potential three-dimensional (3D) applications