100 MHz High Speed SPI Master: Design, Implementation and Study on Limitations of using SPI at High Speed

SPI or Serial Peripheral Interface is among the fastest synchronous serial communication protocols used in embedded systems. High throughput and simplicity of SPI communication has made SPI protocol; a de facto standard. Designs based on FPGAs (Field Programmable Gate Arrays) enhance reusability, flexibility and faster prototyping of digital systems, especially serial buses, which are inevitable in almost all designs. This paper discusses the design and implementation of a 100 MHz High Speed SPI Master Core on FPGA. State machine approach is employed for the RTL (Register Transfer Level) design of the core. The paper also discusses the challenges and limitations of implementing such a high speed SPI bus in digital systems. The SPI Master Core was successfully implemented on Altera Cyclone III FPGA for a speed of 100 MHz

An overview of nanoemulsion characterization via atomic force microscopy

Nanoemulsion-based systems are widely applied in food industries for protecting active ingredients against oxidation and degradation and controlling the release rate of active core ingredients under particular conditions. Visualizing the interface morphology and measuring the interfacial interaction forces of nanoemulsion droplets are essential to tailor and design intelligent nanoemulsion-based systems. Atomic force microscopy (AFM) is being established as an important technique for interface characterization, due to its unique advantages over traditional imaging and surface force-determining approaches. However, there is a gap in knowledge about the applicability of AFM in characterizing the droplet interface properties of nanoemulsions. This review aims to describe the fundamentals of the AFM technique and nanoemulsions, mainly focusing on the recent use of AFM to investigate nanoemulsion properties. In addition, by reviewing interfacial studies on emulsions in general, perspectives for the further development of AFM to study nanoemulsions are also discussed.Peer reviewe

Core interface optimization for multi-core neuromorphic processors

Hardware implementations of Spiking Neural Networks (SNNs) represent a promising approach to edge-computing for applications that require low-power and low-latency, and which cannot resort to external cloud-based computing services. However, most solutions proposed so far either support only relatively small networks, or take up significant hardware resources, to implement large networks. To realize large-scale and scalable SNNs it is necessary to develop an efficient asynchronous communication and routing fabric that enables the design of multi-core architectures. In particular the core interface that manages inter-core spike communication is a crucial component as it represents the bottleneck of Power-Performance-Area (PPA) especially for the arbitration architecture and the routing memory. In this paper we present an arbitration mechanism with the corresponding asynchronous encoding pipeline circuits, based on hierarchical arbiter trees. The proposed scheme reduces the latency by more than 70% in sparse-event mode, compared to the state-of-the-art arbitration architectures, with lower area cost. The routing memory makes use of asynchronous Content Addressable Memory (CAM) with Current Sensing Completion Detection (CSCD), which saves approximately 46% energy, and achieves a 40% increase in throughput against conventional asynchronous CAM using configurable delay lines, at the cost of only a slight increase in area. In addition as it radically reduces the core interface resources in multi-core neuromorphic processors, the arbitration architecture and CAM architecture we propose can be also applied to a wide range of general asynchronous circuits and systems

Development of a CubeSat Conceptual Design Tool and Implementation of the EPS Design Module

This thesis is the product of an effort to develop a CubeSat Conceptual Design Tool for the California Polytechnic State University CubeSat Laboratory. Such a tool is necessary due to inefficiencies with the current conceptual design process. It is being developed to increase accessibility, reduce design time, and promote good systems engineering within CubeSat development. The development of the architecture of a conceptual design tool, the core user-interface element, and the completion of a module for the electrical power subsystem is the focus of this thesis. The architecture is built around different modules to design different subsystems that work in conjunction. The module in the tool was developed to allow a user to size an electrical power subsystem, and that is the basis for future subsystem development. Model-based Systems Engineering was also utilized as an endpoint for the tool’s outputs, and a CubeSat Model has been built for this effort. Validation has been successful on the Conceptual Design Tool as implemented at this time, so the tool it is ready to design CubeSat electrical power subsystems and be expanded upon by other tool developers