A Piecewise Linear Approximation D/A Converter for Small Format LCD Applications

Low power operation is a driving requirement for the advancement of portable consumer electronics. As products get smaller and have more functionality the device integration requirements get tighter. This is certainly true of small format LCD applications like PDAs and cell phones. Recent advances in LCD technology have allowed for advanced circuitry to be built on the glass. This allows for the unique opportunity to integrate the LCD column driver with other circuitry rather than the traditional flip chip mounting on the glass. The integration of these D/A converters with digital circuitry presents a new set of design considerations. These considerations allow for the exploration of non-traditional architectures and algorithms. This work will explore these design considerations in detail and present a novel algorithm for conversion as well as a system implementation of this algorithm. The system implementation is compared to a standard linear converter to weigh the relative advantages of each. A high performance dynamically biased amplifier is developed for use in the D/A converter. This amplifier has a high slew rate while consuming a small amount of quiescent power

Custom Integrated Circuits

Contains table of contents for Part III, table of contents for Section 1 and reports on eleven research projects.IBM CorporationMIT School of EngineeringNational Science Foundation Grant MIP 94-23221Defense Advanced Research Projects Agency/U.S. Army Intelligence Center Contract DABT63-94-C-0053Mitsubishi CorporationNational Science Foundation Young Investigator Award Fellowship MIP 92-58376Joint Industry Program on Offshore Structure AnalysisAnalog DevicesDefense Advanced Research Projects AgencyCadence Design SystemsMAFET ConsortiumConsortium for Superconducting ElectronicsNational Defense Science and Engineering Graduate FellowshipDigital Equipment CorporationMIT Lincoln LaboratorySemiconductor Research CorporationMultiuniversity Research IntiativeNational Science Foundatio

Threshold Voltage Compensation Error in Voltage Programmed AMOLED Displays

A new accurate voltage-programmed pixel circuit for active matrix organic light-emitting diode (AMOLED) displays is presented. Composed of three TFTs and one storage capacitor, the proposed pixel circuit is implemented both in a-Si and a-IGZO TFT technologies for the same pixel size for fair comparison. The simulation result for the a-Si-based design shows that, during a programming time of 90 μs, the pixel circuit was able to compensate for a 3V threshold voltage (Vth) shift of the drive TFT with almost no error. In contrast, the a-IGZO-based pixel circuit, has a larger current error (of around 8%), despite its proven three-fold higher speed.Authors thank to the EPSRC under Project EP/M013650/1

Threshold Voltage Compensation Error in Voltage Programmed AMOLED Displays

© 2005-2012 IEEE. A new accurate voltage-programmed pixel circuit for active-matrix organic light-emitting diode (AMOLED) displays is presented. Composed of three TFTs and one storage capacitor, the proposed pixel circuit is implemented both in a-Si and a-IGZO TFT technologies for the same pixel size for fair comparison. The simulation result for the a-Si-based design shows that, during a programming time of {\hbox{90}}μ \hbox{s} , the pixel circuit was able to compensate for a 3 V threshold voltage (V\rm th) shift of the drive TFT with almost no error. In contrast, the a-IGZO-based pixel circuit, has a larger current error (of around 8%), despite its proven three-fold higher speed.Authors thank to the EPSRC under Project EP/M013650/1

High-Speed and Low-Energy On-Chip Communication Circuits.

Continuous technology scaling sharply reduces transistor delays, while fixed-length global wire delays have increased due to less wiring pitch with higher resistance and coupling capacitance. Due to this ever growing gap, long on-chip interconnects pose well-known latency, bandwidth, and energy challenges to high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, the increased complexity and high level of integration requires higher wire densities, worsening crosstalk noise and power consumption of conventionally repeated interconnects. Such increasing concerns in global on-chip wires motivate circuits to improve wire performance and energy while reducing the number of repeaters. This work presents circuit techniques and investigation for high-performance and energy-efficient on-chip communication in the aspects of encoding, data compression, self-timed current injection, signal pre-emphasis, low-swing signaling, and technology mapping. The improved bus designs also consider the constraints of robust operation and performance/energy gains across process corners and design space. Measurement results from 5mm links on 65nm and 90nm prototype chips validate 2.5-3X improvement in energy-delay product.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/75800/1/jseo_1.pd

A Semi-Empirical Compact Model for IGZO TFT to Assess the Impact of Parasitic Elements in Active Matrix Pixel Designs

In this work, an empirical off-state model was developed for amorphous IGZO TFTs with the purpose of creating a compact model in conjunction with an existing on-state model. The implementation of the compact model was done in Verilog-A to assess the impact of parasitc elements such as source/drain series resistance, and source/drain-to-gate overlap capacitances in a 2T1C pixel circuit. A novel region of operation was presented defined as a bridge between the subthreshold and the on-state regions. Two approaches were followed to solve for the fitting parameters inside this bridge region; an analytical and an empirical approach. The analytical solution provided the insight that there is a point where the derivatives of the on-state and the bridge region are equal. However, this solution showed non-physical behavior at some V_DS bias. Therefore, an empirical approach was followed where experimental data was used to find the V_DS dependence and eliminate the non-physical behavior. Ultimately, the compact model provided a remarkable R^2 in relation to experimental data and allowed for convergence during circuit simulation. The parasitic element assessment was carried out and two different phenomenon were described as they relate to these elements. Charge sharing and rise and fall time were the characteristics that were present with the introduction of parasitic elements. A capacitance ratio of C_ST/C_ov =10.6pF/265.07fF≈40 was used to diminish the former. However, the large capacitances associated in the input of the driver transistor caused the falling transient to be unable to provide full voltage swing. Therefore, proper circuit functionality was not achieved based on the presented design rules. Further work is being done to diminish overlap capacitances such as self-aligned devices