Γ (Gamma): cloud-based analog circuit design system

Includes bibliographical references.2016 Summer.With ever increasing demand for lower power consumption, lower cost, and higher performance, designing analog circuits to meet design specifications has become an increasing challenging task, On one hand, analog circuit designers must have intimate knowledge about the underlining silicon process technology's capability to achieve the desired specifications. On the other hand, they must understand the impact of tweaking circuits to satisfy a given specification on all circuit performance parameters. Analog designers have traditionally learned to tackle design problems with numerous circuit simulations using accurate circuit simulators such as SPICE, and have increasingly relied on trial-and-error approaches to reach a converging point. However, the increased complexity with each generation of silicon technology and high dimensionality of searching for solutions, even for some simple analog circuits, have made trial-and-error approaches extremely inefficient, causing long design cycles and often missed market opportunities. Novel rapid and accurate circuit evaluation methods that are tightly integrated with circuit search and optimization methods are needed to aid design productivity. Furthermore, the current design environment with fully distributed licensing and supporting structures is cumbersome at best to allow efficient and up-to-date support for design engineers. With increasing support and licensing costs, fewer and fewer design centers can afford it. Cloud-based software as a service (SaaS) model provides new opportunities for CAD applications. It enables immediate software delivery and update to customers at very low cost. SaaS tools benefit from fast feedback and sharing channels between users and developers and run on hardware resources tailored and provided for them by software vendors. However, web-based tools must perform in a very short turn-around schedule and be always responsive. A new class of analog design tools is presented in this dissertation. The tools provide effective design aid to analog circuit designers with a dash-board control of many important circuit parameters. Fast and accurate circuit evaluations are achieved using a novel lookup-table transistor models (LUT) with novel built-in features tightly integrated with the search engine to achieve desired speed and accuracy. This enables circuit evaluation time several orders faster than SPICE simulations. The proposed architecture for analog design attempts to break the traditional analog design flow using SPICE based trial-and-error methods by providing designers with useful information about the effects of prior design decisions they have made and potential next steps they can take to meet specifications. Benefiting from the advantages offered by web-hosted architectures, the proposed architecture incorporates SaaS as its operating model. The application of the proposed architecture is illustrated by an analog circuit sizer and optimizer. The Γ (Gamma) sizer and optimizer show how web-based design-decision supporting tool can help analog circuit designers to reduce design time and achieve high quality circuit

On Spike-Timing-Dependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex

In this paper we present a very exciting overlap between emergent nanotechnology and neuroscience, which has been discovered by neuromorphic engineers. Specifically, we are linking one type of memristor nanotechnology devices to the biological synaptic update rule known as spike-time-dependent-plasticity (STDP) found in real biological synapses. Understanding this link allows neuromorphic engineers to develop circuit architectures that use this type of memristors to artificially emulate parts of the visual cortex. We focus on the type of memristors referred to as voltage or flux driven memristors and focus our discussions on a behavioral macro-model for such devices. The implementations result in fully asynchronous architectures with neurons sending their action potentials not only forward but also backward. One critical aspect is to use neurons that generate spikes of specific shapes. We will see how by changing the shapes of the neuron action potential spikes we can tune and manipulate the STDP learning rules for both excitatory and inhibitory synapses. We will see how neurons and memristors can be interconnected to achieve large scale spiking learning systems, that follow a type of multiplicative STDP learning rule. We will briefly extend the architectures to use three-terminal transistors with similar memristive behavior. We will illustrate how a V1 visual cortex layer can assembled and how it is capable of learning to extract orientations from visual data coming from a real artificial CMOS spiking retina observing real life scenes. Finally, we will discuss limitations of currently available memristors. The results presented are based on behavioral simulations and do not take into account non-idealities of devices and interconnects. The aim of this paper is to present, in a tutorial manner, an initial framework for the possible development of fully asynchronous STDP learning neuromorphic architectures exploiting two or three-terminal memristive type devices. All files used for the simulations are made available through the journal web site1

Graphical User Interface (GUI) Development for an Optical Communication Simulator

Modeling and simulation tools have been an integral part of engineering world for a long time. Various Electronic Design Automation (EDA) tools have been extensively used in various industries and research to evaluate the performance of electronic systems. The advancement of such design tools also has influenced the optical communication sector such that there has been a continuous progress on the Photonic Design Automation (PDA) tools. Currently, many software for simulating optical communications are available. However, they are very expensive and conceal the information on how components are modeled. To avoid these constraints, we developed our own PDA software for optical communication. This thesis delves into the development of Graphical User Interface (GUI) of our software. The studied GUI software conforms to the feature of standard simulation software and assists the users to perform a system-level simulation of fiber optic communication. The developed GUI allows the users to design their layout, run the simulation and view the results in the form of data or plot. The GUI is explained with respect to the graphical layout and the interactive features of the components. The detailed structure is described along with the Java library used to build them. The interactive aspects of GUI are investigated, for adding the hierarchical feature to our GUI software. In addition, a plotting tool is created for the GUI. The thesis provides comprehensive information on working principle of GUI for simulation software and describes the addition of plotting tool and hierarchical design in detail

Fault-based Analysis of Industrial Cyber-Physical Systems

The fourth industrial revolution called Industry 4.0 tries to bridge the gap between traditional Electronic Design Automation (EDA) technologies and the necessity of innovating in many indus- trial fields, e.g., automotive, avionic, and manufacturing. This complex digitalization process in- volves every industrial facility and comprises the transformation of methodologies, techniques, and tools to improve the efficiency of every industrial process. The enhancement of functional safety in Industry 4.0 applications needs to exploit the studies related to model-based and data-driven anal- yses of the deployed Industrial Cyber-Physical System (ICPS). Modeling an ICPS is possible at different abstraction levels, relying on the physical details included in the model and necessary to describe specific system behaviors. However, it is extremely complicated because an ICPS is com- posed of heterogeneous components related to different physical domains, e.g., digital, electrical, and mechanical. In addition, it is also necessary to consider not only nominal behaviors but even faulty behaviors to perform more specific analyses, e.g., predictive maintenance of specific assets. Nevertheless, these faulty data are usually not present or not available directly from the industrial machinery. To overcome these limitations, constructing a virtual model of an ICPS extended with different classes of faults enables the characterization of faulty behaviors of the system influenced by different faults. In literature, these topics are addressed with non-uniformly approaches and with the absence of standardized and automatic methodologies for describing and simulating faults in the different domains composing an ICPS. This thesis attempts to overcome these state-of-the-art gaps by proposing novel methodologies, techniques, and tools to: model and simulate analog and multi-domain systems; abstract low-level models to higher-level behavioral models; and monitor industrial systems based on the Industrial Internet of Things (IIOT) paradigm. Specifically, the proposed contributions involve the exten- sion of state-of-the-art fault injection practices to improve the ICPSs safety, the development of frameworks for safety operations automatization, and the definition of a monitoring framework for ICPSs. Overall, fault injection in analog and digital models is the state of the practice to en- sure functional safety, as mentioned in the ISO 26262 standard specific for the automotive field. Starting from state-of-the-art defects defined for analog descriptions, new defects are proposed to enhance the IEEE P2427 draft standard for analog defect modeling and coverage. Moreover, dif- ferent techniques to abstract a transistor-level model to a behavioral model are proposed to speed up the simulation of faulty circuits. Therefore, unlike the electrical domain, there is no extensive use of fault injection techniques in the mechanical one. Thus, extending the fault injection to the mechanical and thermal fields allows for supporting the definition and evaluation of more reliable safety mechanisms. Hence, a taxonomy of mechanical faults is derived from the electrical domain by exploiting the physical analogies. Furthermore, specific tools are built for automatically instru- menting different descriptions with multi-domain faults. The entire work is proposed as a basis for supporting the creation of increasingly resilient and secure ICPS that need to preserve functional safety in any operating context

Novel Computing Paradigms using Oscillators

This dissertation is concerned with new ways of using oscillators to perform computational tasks. Specifically, it introduces methods for building finite state machines (for general-purpose Boolean computation) as well as Ising machines (for solving combinatorial optimization problems) using coupled oscillator networks.But firstly, why oscillators? Why use them for computation?An important reason is simply that oscillators are fascinating. Coupled oscillator systems often display intriguing synchronization phenomena where spontaneous patterns arise. From the synchronous flashing of fireflies to Huygens' clocks ticking in unison, from the molecular mechanism of circadian rhythms to the phase patterns in oscillatory neural circuits, the observation and study of synchronization in coupled oscillators has a long and rich history. Engineers across many disciplines have also taken inspiration from these phenomena, e.g., to design high-performance radio frequency communication circuits and optical lasers. To be able to contribute to the study of coupled oscillators and leverage them in novel paradigms of computing is without question an interesting andfulfilling quest in and of itself.Moreover, as Moore's Law nears its limits, new computing paradigms that are different from mere conventional complementary metal–oxide–semiconductor (CMOS) scaling have become an important area of exploration. One broad direction aims to improve CMOS performance using device technology such as fin field-effect transistors (FinFET) and gate-all-around (GAA) FETs. Other new computing schemes are based on non-CMOS material and device technology, e.g., graphene, carbon nanotubes, memristive devices, optical devices, etc.. Another growing trend in both academia and industry is to build digital application-specific integrated circuits (ASIC) suitable for speeding up certain computational tasks, often leveraging the parallel nature of unconventional non-von Neumann architectures. These schemes seek to circumvent the limitations posed at the device level through innovations at the system/architecture level.Our work on oscillator-based computation represents a direction that is different from the above and features several points of novelty and attractiveness. Firstly, it makes meaningful use of nonlinear dynamical phenomena to tackle well-defined computational tasks that span analog and digital domains. It also differs from conventional computational systems at the fundamental logic encoding level, using timing/phase of oscillation as opposed to voltage levels to represent logic values. These differences bring about several advantages. The change of logic encoding scheme has several device- and system-level benefits related to noise immunity and interference resistance. The use of nonlinear oscillator dynamics allows our systems to address problems difficult for conventional digital computation. Furthermore, our schemes are amenable to realizations using almost all types of oscillators, allowing a wide variety of devices from multiple physical domains to serve as the substrate for computing. This ability to leverage emerging multiphysics devices need not put off the realization of our ideas far into the future. Instead, implementations using well-established circuit technology are already both practical and attractive.This work also differs from all past work on oscillator-based computing, which mostly focuses on specialized image preprocessing tasks, such as edge detection, image segmentation and pattern recognition. Perhaps its most unique feature is that our systems use transitions between analog and digital modes of operation --- unlike other existing schemes that simply couple oscillators and let their phases settle to a continuum of values, we use a special type of injection locking to make each oscillator settle to one of the several well-defined multistable phase-locked states, which we use to encode logic values for computation. Our schemes of oscillator-based Boolean and Ising computation are built upon this digitization of phase; they expand the scope of oscillator-based computing significantly.Our ideas are built on years of past research in the modelling, simulation and analysis of oscillators. While there is a considerable amount of literature (arguably since Christiaan Huygens wrote about his observation of synchronized pendulum clocks in the 17th century) analyzing the synchronization phenomenon from different perspectives at different levels, we have been able to further develop the theory of injection locking, connecting the dots to find a path of analysis that starts from the low-level differential equations of individual oscillators and arrives at phase-based models and energy landscapes of coupled oscillator systems. This theoretical scaffolding is able not only to explain the operation of oscillator-based systems, but also to serve as the basis for simulation and design tools. Building on this, we explore the practical design of our proposed systems, demonstrate working prototypes, as well as develop the techniques, tools and methodologies essential for the process

Physical Aspects of VLSI Design with a Focus on Three-Dimensional Integrated Circuit Applications

This work is on three-dimensional integration (3DI), and physical problems and aspects of VLSI design. Miniaturization and highly complex integrated systems in microelectronics have led to the 3DI development as a promising technological approach. 3DI offers numerous advantages: Size, power consumption, hybrid integration etc., with more thermal problems and physical complexity as trade-offs. We open this work by presenting the design and testing of an example 3DI system, to our knowledge the first self-powering system in a three-dimensional SOI technology. The system uses ambient optical energy harvested by a photodiode array and stored in an integrated capacitor. An on-chip metal interconnect network, beyond its designed role, behaves as a parasitic load vulnerable to electromagnetic coupling. We have developed a spatially-dependent, transient Green's Function based method of calculating the response of an interconnect network to noise. This efficient method can model network delays and noise sensitivity, which are involved problems in both planar and especially in 3DICs. Three-dimensional systems are more susceptible to thermal problems, which also affect VLSI with high power densities, of complex systems and under extreme temperatures. We analytically and experimentally investigate thermal effects in ICs. We study the effects of non-uniform, non-isotropic thermal conductivity of the typically complex IC material system, with a simulator we developed including this complexity. Through our simulations, verified by experiments, we propose a method of cooling or directionally heating IC regions. 3DICs are suited for developing wireless sensor networks, commonly referred to as ``smart dust.'' The ideal smart dust node includes RF communication circuits with on-chip passive components. We present an experimental study of on-chip inductors and transformers as integrated passives. We also demonstrate the performance improvement in 3DI with its lower capacitive loads. 3DI technology is just one example of the intense development in today's electronics, which maintains the need for educational methods to assist student recruitment into technology, to prepare students for a demanding technological landscape, and to raise societal awareness of technology. We conclude this work by presenting three electrical engineering curricula we designed and implemented, targeting these needs among others

Algorithms for Analysis of Nonlinear High-Frequency Circuits

The most efficient simulation solvers use composite procedures that adaptively rearrange computation algorithms to maximize simulation performance. Fast and stable processing optimized for given simulation problem is essential for any modern simulator. It is characteristic for electronic circuit analysis that complexity of simulation is affected by circuit size and used device models. Implementation of electronic device models in program SPICE uses traditional implementation allowing fast computation but further modification of model can be questionable. The first fundamental thesis aim is scalability of the simulation based on the adaptive internal solver composing different algorithms according to properties of simulation problem to maximize simulation performance. In a case of the small circuit as faster solution prove simple, straightforward methods that utilize arithmetic operations without unnecessary condition jumping and memory rearrangements that can not be effectively optimized by a compiler. The limit of small size simulation problems is related to computation machine capabilities. The present day PC sets this limit to fifty independent voltage nodes where inefficiency of calculation procedure does not play any role in overall processor performance. The scalable solver must also be able to handle correctly simulation of large-scale circuits that requires entirely different approach apart to standard size circuits. The unique properties of simulation of the electronic circuits that played until this time only the minor role suddenly gain on significance for circuits with several thousand voltage nodes. In those particular cases, iterative algorithms based on Krylov subspace methods provide better results from the aspect of performance than standard direct methods. This thesis also proposes unique techniques of indexation of the large-scale sparse matrix system. The primary purpose is to reduce memory requirements for storing sparse matrices during simulation computation. The second fundamental thesis aim is automatic adaptivity of device models definition respecting current simulation state and settings. This principle is denoted as Functional Chaining mechanism that is based on the principle of the automatic self-modifying procedure utilizing state-of-the-art functional computation layer during the simulation process. It can significantly improve mapping performance of circuit variables to device models; it also allows autonomous redefinition of simulation algorithms during analysis with an intention to reduce computation time. The core idea is based on utilization of programming principles related to functional programming languages. It is also presents possibilites of reimplementation to the modern object-oriented languages. The third fundamental thesis aim focuses on simulation accuracy and reliability. Arbitrary precision variable types can directly lead to increased simulation accuracy but on the other hand; they can significantly decrease simulation performance. In last chapters, there are several algorithms provided with the claim to provide better simulation accuracy and suppress computation errors of floating point data types.Katedra radioelektronik

Cmos Programmable Time Control Circuit Design For Phased Array Uwb Ground Penetrating Radar Antenna Beamforming

Phased array radar systems employ multiple antennas to create a radar beam that can be steered electronically. By manipulating the relative phase values of feeding signals among different antennas, the effective radiation pattern of the array can be synthesized to enhance the main lobe in a desired direction while suppressing the undesired side lobes in other directions. Hence the radar scanning angles can be electronically controlled without employing the bulky mechanical gimbal structure, which can significantly reduce radar system size, weight and power consumption. In recent years, phased array technologies have received great attentions and are explored in developing many new applications, such as smart communication systems, military radars, vehicular radar, etc. Most of these systems are narrow band systems, where the phase delays are realized with narrow band phase shifter circuits. For the impulse ground penetrating radar however, its operating frequency spans an ultrawide bandwidth. Therefore the traditional phase shifters are not applicable due to their narrow band nature. To resolve the issue, in this study, a true time delay approach is explored which can precisely control time delays for the feeding pulse signals among different antennas in the array. In the design, an on chip programmable delay generator is being developed using Global Foundry 0.18 µm 7 HV high voltage CMOS process. The time delay control is realized by designing a programmable phase locked loop (PLL) circuit which can generate true time delays ranging from 100 ps (picoseconds) to 500 ps with the step size of 25 ps. The PLL oscillator\u27s frequency is programmable from 100MHz to 500MHz through two reconfigurable frequency dividers in the feedback loop. As a result, the antenna beam angle can be synthesized to change from 9.59° to 56.4° with a step of 2.75°, and the 3dB beamwidth is 10°. The power consumption of the time delay circuit is very low, where the supply voltage is 1.8V and the average current is as low as 472uA

Cmos Programmable Time Control Circuit Design For Phased Array Uwb Ground Penetrating Radar Antenna Beamforming

Phased array radar systems employ multiple antennas to create a radar beam that can be steered electronically. By manipulating the relative phase values of feeding signals among different antennas, the effective radiation pattern of the array can be synthesized to enhance the main lobe in a desired direction while suppressing the undesired side lobes in other directions. Hence the radar scanning angles can be electronically controlled without employing the bulky mechanical gimbal structure, which can significantly reduce radar system size, weight and power consumption. In recent years, phased array technologies have received great attentions and are explored in developing many new applications, such as smart communication systems, military radars, vehicular radar, etc. Most of these systems are narrow band systems, where the phase delays are realized with narrow band phase shifter circuits. For the impulse ground penetrating radar however, its operating frequency spans an ultrawide bandwidth. Therefore the traditional phase shifters are not applicable due to their narrow band nature. To resolve the issue, in this study, a true time delay approach is explored which can precisely control time delays for the feeding pulse signals among different antennas in the array. In the design, an on chip programmable delay generator is being developed using Global Foundry 0.18 µm 7 HV high voltage CMOS process. The time delay control is realized by designing a programmable phase locked loop (PLL) circuit which can generate true time delays ranging from 100 ps (picoseconds) to 500 ps with the step size of 25 ps. The PLL oscillator\u27s frequency is programmable from 100MHz to 500MHz through two reconfigurable frequency dividers in the feedback loop. As a result, the antenna beam angle can be synthesized to change from 9.59° to 56.4° with a step of 2.75°, and the 3dB beamwidth is 10°. The power consumption of the time delay circuit is very low, where the supply voltage is 1.8V and the average current is as low as 472uA