2,878 research outputs found
From FPGA to ASIC: A RISC-V processor experience
This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC
Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach
Secara tradisinya, “Field Programmable Gate Array” (FPGA) “Address Register”
(AR) direka menggunakan “full custom”. Dengan keadaan geometri yang mengecut
pada awal proses nod, maka keperluan untuk menimbang semula pendekatan reka
bentuk yang digunakan untuk mereka bentuk FPGA AR diperlukan kerana kitaran
reka bentuk meningkat dan merumitkan yang membawa kepada masa lelaran lanjut
ke atas penutupan masa blok. Terdapat pelbagai jenis cabaran yang terpaksa dihadapi
dalam proses 28nm dan seterusnya sekiranya pendekatan “full custom” masih
digunakan untuk merekabentuk FPGA AR. Oleh itu, pendekatan berasaskan sel
piawai digunakan untuk reka bentuk FPGA AR. Kitaran reka bentuk FPGA AR dapat
dikurangkan dari bulan ke minggu dengan penggunaan kaedah sel piawai. Selain itu,
penutupan masa dapat mengawal senario masa yang lebih. Keputusan menunjukkan
bahawa FPGA AR menggunakan pendekatan berasaskan sel piawai adalah
memenuhi spesifikasi reka bentuk yang diberikan. Di samping itu, jatuhan IR untuk
kuasa dan bumi adalah di bawah 2mV, frekuensi adalah 330 MHz dan keluasan
kawasan adalah 0.975mm2. Sebagai kesimpulan, pendekatan berasaskan sel piawai
memberi pereka lebih banyak masa untuk menyelesaikan isu yang berkaitan dengan
rekabentuk. Di samping itu, perubahan yang disebabkan oleh proses, voltan dan suhu
dapat diperbaiki melalui kaedah pelbagai sudut dan senario ke atas FPGA AR.
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Traditionally, Field Programmable Gate Array (FPGA) Address Register (AR) is
designed using full custom approach. With geometries shrink on advance process
node, there is a need to reconsider the design approach used to design FPGA AR
because of increased design cycle and complexity that lead to more iteration time on
closing block timing. Significant design effort and challenges are required in 28nm
and beyond when using full custom approach. Therefore, standard cell based
approach is used to design the FPGA AR. Design cycle of FPGA AR is reduced from
months to weeks with the automated standard cell based approach. Besides that,
timing closure is able to cover more timing scenarios. Results show that FPGA AR
using standard cell based approach is meeting the given design specification. IR drop
on both power and ground is achieving less than 2mV per rail, frequency of 330MHz
is obtained on FPGA AR and area size is 0.975mm2. In summary, standard cell
based approach gives designer more time to focus on resolving design issues, and
close the design in more timing scenarios which cover more design corners to
improve variation due to process, voltage and temperature
The GENCOD project : Automated generation of Hardware code for safety critical applications on FPGA targets
International audienceGENCOD is a research project for solutions to automated generation of safe code for Field Programmable Gate Arrays (FPGA) targets. The paper will describe typical ASIC/FPGA workflow, and current implementation for airborne electronic hardware design. Major stakes in certification for airborne electronic hardware will be discussed. The next part will detail the project, the proposed workflow and the associated tools. We will present the current experimentations. Finally, the conclusion will expose advantages and drawbacks of such approach
SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies
As the ASIC design cost becomes affordable only for very large-scale productions, the FPGA technology is currently becoming the leading technology for those applications that require a small-scale production. FPGAs can be considered as a technology crossing between hardware and software. Only a small-number of standards for the design of safety-critical systems give guidelines and recommendations that take the peculiarities of the FPGA technology into consideration. The main contribution of this paper is an overview of the existing design standards that regulate the design and verification of FPGA-based systems in safety-critical application fields. Moreover, the paper proposes a survey of significant published research proposals and existing industrial guidelines about the topic, and collects and reports about some lessons learned from industrial and research projects involving the use of FPGA devices
Internationalisation of Innovation: Why Chip Design Moving to Asia
This paper will appear in International Journal of Innovation Management, special issue in honor of Keith Pavitt, (Peter Augsdoerfer, Jonathan Sapsed, and James Utterback, guest editors), forthcoming. Among Keith Pavitt's many contributions to the study of innovation is the proposition that physical proximity is advantageous for innovative activities that involve highly complex technological knowledge But chip design, a process that creates the greatest value in the electronics industry and that requires highly complex knowledge, is experiencing a massive dispersion to leading Asian electronics exporting countries. To explain why chip design is moving to Asia, the paper draws on interviews with 60 companies and 15 research institutions that are doing leading-edge chip design in Asia. I demonstrate that "pull" and "policy" factors explain what attracts design to particular locations. But to get to the root causes that shift the balance in favor of geographical decentralization, I examine "push" factors, i.e. changes in design methodology ("system-on-chip design") and organization ("vertical specialization" within global design networks). The resultant increase in knowledge mobility explains why chip design - that, in Pavitt's framework is not supposed to move - is moving from the traditional centers to a few new specialized design clusters in Asia. A completely revised and updated version has been published as: " Complexity and Internationalisation of Innovation: Why is Chip Design Moving to Asia?," in International Journal of Innovation Management, special issue in honour of Keith Pavitt, Vol. 9,1: 47-73.
Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 2: Army fault tolerant architecture design and analysis
Described here is the Army Fault Tolerant Architecture (AFTA) hardware architecture and components and the operating system. The architectural and operational theory of the AFTA Fault Tolerant Data Bus is discussed. The test and maintenance strategy developed for use in fielded AFTA installations is presented. An approach to be used in reducing the probability of AFTA failure due to common mode faults is described. Analytical models for AFTA performance, reliability, availability, life cycle cost, weight, power, and volume are developed. An approach is presented for using VHSIC Hardware Description Language (VHDL) to describe and design AFTA's developmental hardware. A plan is described for verifying and validating key AFTA concepts during the Dem/Val phase. Analytical models and partial mission requirements are used to generate AFTA configurations for the TF/TA/NOE and Ground Vehicle missions
Interchange of electronic design through VHDL and EIS
The need for both robust and unambiguous electronic designs is a direct requirement of the astonishing growth in design and manufacturing capability during recent years. In order to manage the plethora of designs, and have the design data both interchangeable and interoperable, the Very High Speed Integrated Circuits (VHSIC) program is developing two major standards for the electronic design community. The VHSIC Hardware Description Language (VHDL) is designed to be the lingua franca for transmission of design data between designers and their environments. The Engineering Information System (EIS) is designed to ease the integration of data betweeen diverse design automation systems. This paper describes the rationale for the necessity for these two standards and how they provide a synergistic expressive capability across the macrocosm of design environments
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