Design of a fault tolerant airborne digital computer. Volume 1: Architecture

This volume is concerned with the architecture of a fault tolerant digital computer for an advanced commercial aircraft. All of the computations of the aircraft, including those presently carried out by analogue techniques, are to be carried out in this digital computer. Among the important qualities of the computer are the following: (1) The capacity is to be matched to the aircraft environment. (2) The reliability is to be selectively matched to the criticality and deadline requirements of each of the computations. (3) The system is to be readily expandable. contractible, and (4) The design is to appropriate to post 1975 technology. Three candidate architectures are discussed and assessed in terms of the above qualities. Of the three candidates, a newly conceived architecture, Software Implemented Fault Tolerance (SIFT), provides the best match to the above qualities. In addition SIFT is particularly simple and believable. The other candidates, Bus Checker System (BUCS), also newly conceived in this project, and the Hopkins multiprocessor are potentially more efficient than SIFT in the use of redundancy, but otherwise are not as attractive

ARQ protocol for joint source and channel coding and its applications

Shannon\u27s separation theorem states that for transmission over noisy channels, approaching channel capacity is possible with the separation of source and channel coding. Practically, the situation is different. Infinite size blocks are needed to achieve this theoretical limit. Also, time-varying channels require a different approach. This leads to many approaches for source and channel coding. This dissertation will address a joint source and channel coding that suits Automatic Repeat Request (ARQ) application and applies it to packet switching networks. Following aspects of the proposed joint source and channel coding approach will be presented: The design of the proposed joint source and channel coding scheme. The approach is based on a variable length coding scheme which adapts the arithmetic coding process for joint source and channel coding. The protocol using this joint source and channel coding scheme in communication systems. The error recovery technique of the proposed scheme is presented. The application of the scheme and protocol. The design is applied to wireless TCP network and real-time video transmissions. The coding scheme embeds the redundancy needed for error detection in source coding stage. The self-synchronization property of lossless compression is utilized by decoder to detect channel errors. With this approach, error detection may be delayed. The delay in detection is referred to as error propagation distance. This work analyzes the distribution of error propagation distance. The error recovery technique of this joint source and channel coding for ARQ (JARQ) protocol is analyzed. Throughput is studied using signal flow graph for both independent channel and nonindependent channels. A packet combining technique is presented which utilizes the non-uniform distribution of error propagation distance to increase the throughput. The proposed scheme may be applied to many areas. In particular, two applications are discussed. A TCP/JARQ protocol stack is introduced and the coordination between TCP and JARQ layers is discussed to maximize system performance. By limiting the number of retransmission, the proposed scheme is applied to real-time transmission to meet timing requirement

QYMSYM: A GPU-Accelerated Hybrid Symplectic Integrator That Permits Close Encounters

We describe a parallel hybrid symplectic integrator for planetary system integration that runs on a graphics processing unit (GPU). The integrator identifies close approaches between particles and switches from symplectic to Hermite algorithms for particles that require higher resolution integrations. The integrator is approximately as accurate as other hybrid symplectic integrators but is GPU accelerated.Comment: 17 pages, 2 figure

Analytical tools for optimizing the error correction performance of arithmetic codes

International audienceIn joint source-channel arithmetic coding (JSCAC) schemes, additional redundancy may be introduced into an arithmetic source code in order to be more robust against transmission errors. The purpose of this work is to provide analytical tools to predict and evaluate the effectiveness of that redundancy. Integer binary Arithmetic Coding (AC) is modeled by a reduced-state automaton in order to obtain a bit-clock trellis describing the encoding process. Considering AC as a trellis code, distance spectra are then derived. In particular, an algorithm to compute the free distance of an arithmetic code is proposed. The obtained code properties allow to compute upper bounds on both bit error and symbol error probabilities and thus provide an objective criterion to analyze the behavior of JSCAC schemes when used on noisy channels. This criterion is then exploited to design efficient error-correcting arithmetic codes. Simulation results highlight the validity of the theoretical error bounds and show that for equivalent rate and complexity, a simple optimization yields JSCACs that outperform classical tandem schemes at low to medium SNR