DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

Emerging applications of integrated optical microcombs for analogue RF and microwave photonic signal processing

We review new applications of integrated microcombs in RF and microwave photonic systems. We demonstrate a wide range of powerful functions including a photonic intensity high order and fractional differentiators, optical true time delays, advanced filters, RF channelizer and other functions, based on a Kerr optical comb generated by a compact integrated microring resonator, or microcomb. The microcomb is CMOS compatible and contains a large number of comb lines, which can serve as a high performance multiwavelength source for the transversal filter, thus greatly reduce the cost, size, and complexity of the system. The operation principle of these functions is theoretically analyzed, and experimental demonstrations are presented.Comment: 16 pages, 8 figures, 136 References. Photonics West 2018 invited paper, expanded version. arXiv admin note: substantial text overlap with arXiv:1710.00678, arXiv:1710.0861

High performance photonic microwave filters based on a 50GHz optical soliton crystal Kerr micro-comb

We demonstrate a photonic radio frequency (RF) transversal filter based on an integrated optical micro-comb source featuring a record low free spectral range of 49 GHz yielding 80 micro-comb lines across the C-band. This record-high number of taps, or wavelengths for the transversal filter results in significantly increased performance including a QRF factor more than four times higher than previous results. Further, by employing both positive and negative taps, an improved out-of-band rejection of up to 48.9 dB is demonstrated using Gaussian apodization, together with a tunable centre frequency covering the RF spectra range, with a widely tunable 3-dB bandwidth and versatile dynamically adjustable filter shapes. Our experimental results match well with theory, showing that our transversal filter is a competitive solution to implement advanced adaptive RF filters with broad operational bandwidths, high frequency selectivity, high reconfigurability, and potentially reduced cost and footprint. This approach is promising for applications in modern radar and communications systems.Comment: 19 pages, 12 figures, 107 reference

The Chameleon Architecture for Streaming DSP Applications

We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool

BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations

Objective: The advent of High-Performance Computing (HPC) in recent years has led to its increasing use in brain study through computational models. The scale and complexity of such models are constantly increasing, leading to challenging computational requirements. Even though modern HPC platforms can often deal with such challenges, the vast diversity of the modeling field does not permit for a single acceleration (or homogeneous) platform to effectively address the complete array of modeling requirements. Approach: In this paper we propose and build BrainFrame, a heterogeneous acceleration platform, incorporating three distinct acceleration technologies, a Dataflow Engine, a Xeon Phi and a GP-GPU. The PyNN framework is also integrated into the platform. As a challenging proof of concept, we analyze the performance of BrainFrame on different instances of a state-of-the-art neuron model, modeling the Inferior- Olivary Nucleus using a biophysically-meaningful, extended Hodgkin-Huxley representation. The model instances take into account not only the neuronal- network dimensions but also different network-connectivity circumstances that can drastically change application workload characteristics. Main results: The synthetic approach of three HPC technologies demonstrated that BrainFrame is better able to cope with the modeling diversity encountered. Our performance analysis shows clearly that the model directly affect performance and all three technologies are required to cope with all the model use cases.Comment: 16 pages, 18 figures, 5 table

Dependable reconfigurable multi-sensor poles for security

Wireless sensor network poles for security monitoring under harsh environments require a very high dependability as they are safety-critical [1]. An example of a multi-sensor pole is shown. Crucial attribute in these systems for security, especially in harsh environment, is a high robustness and guaranteed availability during lifetime. This environment could include molest. In this paper, two approaches are used which are applied simultaneously but are developed in different projects. \u

Free spectral range electrical tuning of a high quality on-chip microcavity

Reconfigurable photonic circuits have applications ranging from next-generation computer architectures to quantum networks, coherent radar and optical metamaterials. However, complete reconfigurability is only currently practical on millimetre-scale device footprints. Here, we overcome this barrier by developing an on-chip high quality microcavity with resonances that can be electrically tuned across a full free spectral range (FSR). FSR tuning allows resonance with any source or emitter, or between any number of networked microcavities. We achieve it by integrating nanoelectronic actuation with strong optomechanical interactions that create a highly strain-dependent effective refractive index. This allows low voltages and sub-nanowatt power consumption. We demonstrate a basic reconfigurable photonic network, bringing the microcavity into resonance with an arbitrary mode of a microtoroidal optical cavity across a telecommunications fibre link. Our results have applications beyond photonic circuits, including widely tuneable integrated lasers, reconfigurable optical filters for telecommunications and astronomy, and on-chip sensor networks.Comment: Main text: 7 pages, 3 figures. Supplementary information: 7 pages, 9 figure