Through-silicon-via-aware prediction and physical design for multi-granularity 3D integrated circuits

The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.PhDCommittee Chair: Lim, Sung Kyu; Committee Member: Bakir, Muhannad; Committee Member: Kim, Hyesoon; Committee Member: Lee, Hsien-Hsin Sean; Committee Member: Mukhopadhyay, Saiba

Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts

The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored. In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts. In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied. In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively. In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality.PhDCommittee Chair: Lim, Sung Kyu; Committee Member: Bakir, Muhannad; Committee Member: Kim, Hyesoon; Committee Member: Mukhopadhyay, Saibal; Committee Member: Swaminathan, Madhava

Architecture-Aware Configuration and Scheduling of Matrix Multiplication on Asymmetric Multicore Processors

Asymmetric multicore processors (AMPs) have recently emerged as an appealing technology for severely energy-constrained environments, especially in mobile appliances where heterogeneity in applications is mainstream. In addition, given the growing interest for low-power high performance computing, this type of architectures is also being investigated as a means to improve the throughput-per-Watt of complex scientific applications. In this paper, we design and embed several architecture-aware optimizations into a multi-threaded general matrix multiplication (gemm), a key operation of the BLAS, in order to obtain a high performance implementation for ARM big.LITTLE AMPs. Our solution is based on the reference implementation of gemm in the BLIS library, and integrates a cache-aware configuration as well as asymmetric--static and dynamic scheduling strategies that carefully tune and distribute the operation's micro-kernels among the big and LITTLE cores of the target processor. The experimental results on a Samsung Exynos 5422, a system-on-chip with ARM Cortex-A15 and Cortex-A7 clusters that implements the big.LITTLE model, expose that our cache-aware versions of gemm with asymmetric scheduling attain important gains in performance with respect to its architecture-oblivious counterparts while exploiting all the resources of the AMP to deliver considerable energy efficiency

On thermal sensor calibration and software techniques for many-core thermal management

The high power density of a many-core processor results in increased temperature which negatively impacts system reliability and performance. Dynamic thermal management applies thermal-aware techniques at run time to avoid overheating using temperature information collected from on-chip thermal sensors. Temperature sensing and thermal control schemes are two critical technologies for successfully maintaining thermal safety. In this dissertation, on-line thermal sensor calibration schemes are developed to provide accurate temperature information. Software-based dynamic thermal management techniques are proposed using calibrated thermal sensors. Due to process variation and silicon aging, on-chip thermal sensors require periodic calibration before use in DTM. However, the calibration cost for thermal sensors can be prohibitively high as the number of on-chip sensors increases. Linear models which are suitable for on-line calculation are employed to estimate temperatures at multiple sensor locations using performance counters. The estimated temperature and the actual sensor thermal profile show a very high similarity with correlation coefficient ~0.9 for SPLASH2 and SPEC2000 benchmarks. A calibration approach is proposed to combine potentially inaccurate temperature values obtained from two sources: thermal sensor readings and temperature estimations. A data fusion strategy based on Bayesian inference, which combines information from these two sources, is demonstrated. The result shows the strategy can effectively recalibrate sensor readings in response to inaccuracies caused by process variation and environmental noise. The average absolute error of the corrected sensor temperature readings is A dynamic task allocation strategy is proposed to address localized overheating in many-core systems. Our approach employs reinforcement learning, a dynamic machine learning algorithm that performs task allocation based on current temperatures and a prediction regarding which assignment will minimize the peak temperature. Our results show that the proposed technique is fast (scheduling performed in \u3c1 \u3ems) and can efficiently reduce peak temperature by up to 8 degree C in a 49-core processor (6% on average) versus a leading competing task allocation approach for a series of SPLASH-2 benchmarks. Reinforcement learning has also been applied to 3D integrated circuits to allocate tasks with thermal awareness

Electro-Thermal Codesign in Liquid Cooled 3D ICs: Pushing the Power-Performance Limits

The performance improvement of today's computer systems is usually accompanied by increased chip power consumption and system temperature. Modern CPUs dissipate an average of 70-100W power while spatial and temporal power variations result in hotspots with even higher power density (up to 300W/cm^2). The coming years will continue to witness a significant increase in CPU power dissipation due to advanced multi-core architectures and 3D integration technologies. Nowadays the problems of increased chip power density, leakage power and system temperatures have become major obstacles for further improvement in chip performance. The conventional air cooling based heat sink has been proved to be insufficient for three dimensional integrated circuits (3D-ICs). Hence better cooling solutions are necessary. Micro-fluidic cooling, which integrates micro-channel heat sinks into silicon substrates of the chip and uses liquid flow to remove heat inside the chip, is an effective active cooling scheme for 3D-ICs. While the micro-fluidic cooling provides excellent cooling to 3D-ICs, the associated overhead (cooling power consumed by the pump to inject the coolant through micro-channels) is significant. Moreover, the 3D-IC structure also imposes constraints on micro-channel locations (basically resource conflict with through-silicon-vias TSVs or other structures). In this work, we investigate optimized micro-channel configurations that address the aforementioned considerations. We develop three micro-channel structures (hotspot optimized cooling configuration, bended micro-channel and hybrid cooling network) that can provide sufficient cooling to 3D-IC with minimum cooling power overhead, while at the same time, compatible with the existing electrical structure such as TSVs. These configurations can achieve up to 70% cooling power savings compared with the configuration without any optimization. Based on these configurations, we then develop a micro-fluidic cooling based dynamic thermal management approach that maintains the chip temperature through controlling the fluid flow rate (pressure drop) through micro-channels. These cooling configurations are designed after the electrical parts, and therefore, compatible with the current standard IC design flow. Furthermore, the electrical, thermal, cooling and mechanical aspects of 3D-IC are interdependent. Hence the conventional design flow that designs the cooling configuration after electrical aspect is finished will result in inefficiencies. In order to overcome this problem, we then investigate electrical-thermal co-design methodology for 3D-ICs. Two co-design problems are explored: TSV assignment and micro-channel placement co-design, and gate sizing and fluidic cooling co-design. The experimental results show that the co-design enables a fundamental power-performance improvement over the conventional design flow which separates the electrical and cooling design. For example, the gate sizing and fluidic cooling co-design achieves 12% power savings under the same circuit timing constraint and 16% circuit speedup under the same power budget

A decision support environment for behavioral synthesis

We present a specification of a general environment for behavioral synthesis centered around the user/designer as the primary motivator for decisions in design development. At each stage of the design process, the user can perform transformations on the design description through graphical user interfaces. Quality measures, physical estimates, and design hints are given to the user at each stage

The MSFC complementary metal oxide semiconductor (including multilevel interconnect metallization) process handbook

The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included