70,172 research outputs found

    Questa Capabilities Demonstration Set

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    Tato bakalářská práce se zabývá prezentací práce s verifikační platformou Questa od společnosti Mentor Graphics při verifikaci číslicových obvodů. V úvodu práce jsou poskytnuty základní informace o principech verifikace založené na formálních tvrzeních. V rámci práce je uveden popis verifikačního nástroje Questa AutoCheck, který slouží k automatické kontrole obvodů a verifikačního nástroje Questa Formal, který slouží statické formální verifikaci číslicových obvodů.  Na sadě příkladů užití jsou demonstrovány jednotlivé možnosti využití nástrojů při verifikaci konkrétního číslicového obvodu. V závěru práce jsou vyhodnoceny možnosti aplikace těchto nástrojů v praxi.This bachelor thesis deals with presentation of capabilities of verification platform Questa Static from Mentor Graphics company. The basic information about the principles of assertion based verification is provided in the beginning.  The thesis describes Questa AutoCheck verification tool which is used for automatic verification of integrated circuits and Questa Formal verification tool which is used for static formal verification of integrated circuits. The set of examples is given to demonstrate various options of using these tools for verification of a concrete integrated circuit design. In conclusion, the thesis evaluates the possibilities of application of these tools in verification process.

    Reverse Engineering Integrated Circuits Using Finite State Machine Analysis

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    Due to the lack of a secure supply chain, it is not possible \ to fully trust the integrity of electronic devices. Current \ methods of verifying integrated circuits are either destructive \ or non-specific. Here we expand upon prior work, in \ which we proposed a novel method of reverse engineering \ the finite state machines that integrated circuits are built \ upon in a non-destructive and highly specific manner. In \ this paper, we present a methodology for reverse engineering \ integrated circuits, including a mathematical verification of \ a scalable algorithm used to generate minimal finite state \ machine representations of integrated circuits

    Surface inspection: Research and development

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    Surface inspection techniques are used for process learning, quality verification, and postmortem analysis in manufacturing for a spectrum of disciplines. First, trends in surface analysis are summarized for integrated circuits, high density interconnection boards, and magnetic disks, emphasizing on-line applications as opposed to off-line or development techniques. Then, a closer look is taken at microcontamination detection from both a patterned defect and a particulate inspection point of view

    Time Constrained Verification of Analog Circuits using Model-Checking Algorithms

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    In this contribution we present algorithms for model checking of analog circuits enabling the specification of time constraints. Furthermore, a methodology for defining time-based specifications is introduced. An already known method for model checking of integrated analog circuits has been extended to take into account time constraints. The method will be presented using three industrial circuits. The results of model checking will be compared to verification by simulation

    Limits on Fundamental Limits to Computation

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    An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

    A design methodology for application specific fuzzy integrated circuits

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    The main objective of this contribution is to present a design methodology for application specific fuzzy integrated circuits. This methodology is based on an specific architecture and a user-friendly design environment which enables the specification, verification and synthesis of fuzzy systems taking into account conceptual as well as microelectronics considerations

    Timing Verification of Adaptive Integrated Circuits

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    An adaptive circuit can perform built-in self-detection of timing variations and accordingly adjust itself to avoid timing violations. Compared with conventional over-design approach, adaptive circuit design is conceptually advantageous in terms of power-efficiency. Although the advantage has been witnessed in numerous previous works including test chips, adaptive design is far from being widely used in practice. A key reason is the lack of corresponding timing verification support. We developed new timing analysis techniques to fill this void. A main challenge is the large runtime complexity due to numerous adaptivity configurations. We propose several pruning and reduction techniques and apply them in conjunction with statistical static timing analysis (SSTA). The proposed method is validated on benchmark circuits including the recent ISPD'13 suite, which has circuit as large as 150K gates. The results show that our method can achieve orders of magnitude speed-up over Monte Carlo simulation with about the same accuracy. It is also several times faster than an exhaustive application of SSTA

    OVM compliant verification for a wishbone compatible i2c master controller core

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    Increasing design complexity and concurrency of Integrated Circuits has made traditional directed testbenches an unworkable solution for testing. Today, testing as a word has been substituted with verification. Verification engineers have to ensure what goes to the factory for manufacturing is an accurate representation of the design specification. Inter Integrated Circuit (I2C) bus is a very widely used communication protocol in embedded system design due to its hardware simplicity and high data transfer rates capability. Most ICs incorporate I2C interface. Thus the ASIC design process of these ICs calls for robust, independent and exhaustive verification to reduce the risks of their failures. Open Verification Methodology (OVM) is an open source verification methodology library intended to run on multiple platforms and be supported by multiple EDA vendors. This thesis attempts to study and hence introduces a comprehensive verification environment for the latest specifications of the I2C bus protocol realized in the OVM platform, a new industry standard for comprehensive verification due to its rich base classes and OOP features. This work has been challenging since very few work has been reported in this domain for reference
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