260 research outputs found
Integrated radio frequency synthetizers for wireless applications
This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump.
This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed.
The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance.
The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe
A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme
An 80 MHz bandpass filter with a tunable quality factor of 16∼44 using an improved transconductor circuit is presented. A noise optimized biquad structure for high-Q, high- frequency bandpass filter is proposed. The quality factor of the filter is tuned using a new quality factor locked loop algorithm. It was shown that a second-order quality factor locked loop is necessary and sufficient to tune the quality factor of a bandpass filter with zero steady state error. The accuracy, mismatch, and sensitivty analysis of the new tuning scheme was performed and analyzed. Based on the proposed noise optimized filter structure and new quality factor tuning scheme, a biquad filter was designed and fabricated in 0.25 μm BiCMOS process. The measured results show that the biquad filter achieves a SNR of 45 dB at IMD of 40 dB. The P-1dB compression point and IIP3 of the filter are -10 dBm and -2.68 dBm, respectively. The proposed biquad filter and quality factor tuning scheme consumes 58mW and 13 mW of power at 3.3 V supply.Ph.D.Committee Chair: Allen Phillip; Committee Member: Hasler Paul; Committee Member: Keezer David; Committee Member: Kenny James; Committee Member: Pan Ronghu
Piezoelectric Transformer and Hall-Effect Based Sensing and Disturbance Monitoring Methodology for High-Voltage Power Supply Lines
Advancements in relaying algorithms have led to an accurate and robust protection system widely used in power distribution. However, in low power sections of relaying systems, standard voltage and current measurement techniques are still used. These techniques have disadvantages like higher cost, size, electromagnetic interference, resistive losses and measurement errors and hence provide a number of opportunities for improvement and integration. We present a novel microsystem methodology to sense low-power voltage and current signals and detect disturbances in high-voltage power distribution lines. The system employs dual sensor architecture that consists of a piezoelectric transformer in combination with Hall-effect sensor, used to detect the disturbances whose harmonics are in the kHz frequency range.
Our numerical analysis is based on three-dimensional finite element models of the piezoelectric transformer (PT) and the principle of Hall-effect based “Integrated Magnetic Concentrator (IMC)” sensor. This model is verified by using experimental data recorded in the resonant frequency and low frequency regions of operation of PT for voltage sensing. Actual measurements with the commercial IMC sensor too validate the modelling results.
These results describe a characteristic low frequency behaviour of rectangular piezoelectric transformer, which enables it to withstand voltages as high as 150V. In the frequency range of 10Hz to 250Hz, the PT steps down 10-150V input with a linearity of ±1%. The recorded group delay data shows that propagation delay through PT reduces to few microseconds above 1kHz input signal frequency. Similarly, the non-intrusive current sensor detects current with a response time of 8μs and converts the current into corresponding output voltage. These properties, in addition to frequency spectrum of voltage and current input signals, have been used to develop a signal processing and fault detection system for two real-time cases of faults to produce a 6-bit decision logic capable of detecting various types of line disturbances in less than 3ms of delay
INTEGRATED CHIRPED-GRATING SPECTROMETER-ON-A-CHIP
In this dissertation we demonstrate a new structure based on waveguide coupling atop a silicon wafer using a chirped grating to provide the dispersion that leads to a high-resolution, compact, fully integrable and CMOS-compatible spectrometer. Light is both analyzed and detected in a single, completely monolithic component which enables realizing a high-resolution portable spectrometer with an extremely compact footprint. The structure is comprised of a SiO2/Si3N4/SiO2 waveguide on top of a silicon wafer. Grating regions are fabricated on the top cladding of the waveguide. The input light is incident on a chirped grating area known as the collection area. Because of the local variation of the grating pitch across the collection area, different wavelengths of light are coupled into the waveguide at different lateral positions across the collection area. Guided light is then outcoupled through second grating region known as the detection area to the array of photodiodes placed either atop the second grating region or below the second grating region in silicon chip. Therefore, spectral information is encoded in the chirped grating coupler, which is fabricated in a single lithography step, independent of the number of channels. For these initial experiments, a separate detection array was used. In future iterations, these detectors can be integrated into the underlying silicon, resulting in a fully integrated spectrometer on a chip. Varying the input angle of the light will vary the measurement spectral range. This will result in an inexpensive spectrometer on chip, with adjustable resolution and spectral coverage controlled by the grating chirp and the input angle
A simple sinusoidal quadrature oscillator using a single active element
This study describes a simple design for a single active element sinusoidal oscillator with a quadrature signal. A current conveyor transconductance amplifier (CCTA), a single resistor, and two grounded capacitors are used in the first circuit. The second circuit is improved by using a current-controlled current conveyor transconductance amplifier (CCCCTA) and two grounded capacitors without a passive resistor, which means the grounded capacitor is suitably implemented for the IC fabrication. The oscillation condition and frequency of both circuits can be controlled using the same method that concurrently adjusts the DC bias current and the resistance as well as the oscillation frequency can be independently adjusted by capacitances. The CCTA is achieved by cascading the integrated circuits (IC) AD844 and LM13700, made by Analog Devices Corporation and Texas Instruments, respectively, which are available for commercial purchase. The sinusoidal quadrature signals in the time-domain and frequency-domain can be shown with computer simulations and the results of experiments. The Monte Carlo Analysis is also utilized to examine the oscillation frequency with the influence of passive element tolerance errors. The predicted oscillation frequency has a standard variation of about 20.04 kHz, with a maximum frequency of approximately 346.89 kHz and a minimum frequency of approximately 259.09 kHz. In addition, the mean and median frequencies are 296.10 and 293.98 kHz, respectively. The results of this study indicate that computer simulation and experiment are similar to a theoretical analysis, making them suiTable for use in the teaching of electrical and electronic engineerin
Phase modulating interferometry with stroboscopic illumination for characterization of MEMS
This Thesis proposes phase modulating interferometry as an alternative to phase stepping and phase-shifting interferometry for use in the shape and displacement characterization of microelectromechanical systems (MEMS) [Creath, 1988; de Groot, 1995a; Furlong and Pryputniewicz, 2003]. A phase modulating interferometer is developed theoretically with the use of a stroboscopic illumination source and implemented on a Linnik configured interferometer using a software control package developed in the LabVIEWâ„¢ programming environment. Optimization of the amplitude and phase of the sinusoidal modulation source is accomplished through the investigation and minimization of errors created by additive noise effects on the recovered optical phase. A spatial resolution of 2.762 µm over a 2.97x2.37 mm field of view has been demonstrated with 4x magnification objectives within the developed interferometer. The measurement resolution lays within the design tolerance of a 500Ã… ±2.5% thick NIST traceable gold film and within 0.2 nm of data acquired under low modulation frequency phase stepping interferometry on the same physical system. The environmental stability of the phase modulating interferometer is contrasted to the phase stepping interferometer, exhibiting a mean wrapped phase drift of 40.1 mrad versus 91 mrad under similar modulation frequencies. Shape and displacement characterization of failed µHexFlex devices from MIT\u27s Precision Compliant Systems Laboratory is presented under phase modulating and phase stepping interferometry. Shape characterization indicates a central stage displacement of up to 7.6 µm. With a linear displacement rate of 0.75 Ã…/mV under time variant load conditions as compared to a nominal rate of 1.0 Ã…/mV in an undamaged structure [Chen and Culpepper, 2006]
Arbitrarily Tunable Phase Shift in Low-Frequency Multiphase Oscillator
A special electronically tunable multiphase oscillator with arbitrarily and continuously adjustable phase shifts is introduced. Our design assumes to set the phase around the asymptotical limit of 180.. These features cannot be easily achieved in a standard way, i.e., any simple single-phase oscillator supplemented by a first-order adjustable all-pass (AP) section (shifter). The proposed design uses an electronically linearly tunable quadrature oscillator with a frequency range from 0.98 up to 12.54 kHz. It also offers multiples of 45. as the initial setting of the phase shift tuning region. The example of operation shows the adjustment of the phase shift at a specific frequency (10 kHz) within the range of +/- 45 degrees. and around -180 degrees, -135 degrees, and -90 degrees. This variability is not available in standard cases without the use of several AP sections. The current value of the phase shift of the presented oscillator is electronically controlled and does not influence the oscillation frequency and condition of oscillation. Output levels of produced signals are not influenced by this tuning process and are in the range of several hundreds of mV. Two applications of the oscillator are proposed. The first one focuses on low-bitrate modulation systems [phase shift keying (PSK)] while in the second one, our circuit represents a source of phase-adjustable signals in acoustic experiments. Discrete passive elements and active devices (special multipliers having current output terminals, unity-gain differential voltage buffers) fabricated in 0.35 mu m I3T25 ON Semiconductor 3.3 V CMOS process are used in experimental verification
Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers
In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level.
At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs.
At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers.
The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007
CMOS Current Feedback Operational Amplifier-Based Relaxation Generator for Capacity to Voltage Sensor Interface
This paper presents a simple relaxation generator, suitable for a sensor interface, operating as a transducer of capacitance to frequency/period. The proposed circuit employs a current feedback operational amplifier, fabricated in I3T25 0.35 m ON Semiconductor CMOS process, and four passive elements including a grounded capacitor (the sensed parameter). It offers a low-impedance voltage output of the generated square wave. Additional frequency to DC voltage converter offers output information in the form of voltage. The experimental capacitance variation from 6.8 nF to 100 nF yields voltage change in the range from 21 mV to 106 mV with error below 5% and sensitivity 0.912 mV/nF evaluated over the full range of change. These values are in good agreement with simulation results obtained from the Mathcad model of frequency to DC voltage transducer passive circuit
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