127 research outputs found

    Wireless Power Transfer System for Battery-Less Body Implantable Devices

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    Department of Electrical EngineeringAs the life expectancy is increased and the welfare is promoted, researches on the body implantable medical devices (BIMD) are actively being carried out, and products providing more various functions are being released. On the other hand, due to these various functions, the power consumption of the BIMD is also increased, so that the primary battery alone cannot provide sufficient power for the devices. The limited capacity and life time of batteries force patients to make an additional payment and suffering for the power supply of the BIMD. Wireless power transfer technology is the technology which has been making remarkable progress mainly in wireless charging for personal portable devices and electric vehicles. Convergence of wireless power transfer technology (WPT) and rechargeable battery can extend the life time of the BIMD and reduce the suffering and the cost for battery replacements. Furthermore, WPT enables the devices which do not need to operate consistently such as body implantable sensor devices to be used without batteries. In this dissertation, techniques to support WPT for BIMD are introduced and proposed. First, basic researches on magnetic coupled WPT are presented. The basics which are important factors to analyze power transmission are introduced. In addition, circuits that make up the WPT system are described. There are three common technical challenges in WPT. Those are efficiency degradation on coil geometry, voltage gain variation with coil geometry, and power losses in WPT. The common challenges are discussed in chapter II. Moreover, additional challenges which are arisen in WPT for BIMD and approaches to resolve the challenges are addressed in chapter II. Then, efficiency improvement techniques and control techniques in WPT are presented in chapter III. The presented techniques to improve efficiency are applied in coil parts and circuit parts. In coil parts, efficiency enhancement technique by geometric variation is proposed. In circuit parts, instantaneous power consuming technique for step-down converter is suggested. Li-ion battery charger is also discussed in chapter III. Additionally, the wireless controlled constant current / constant voltage charging mode and the proposed step charging method are described. After that, WPT system for BIMD is discussed one by one with the proposed techniques for each part in chapter IV. A load transformation is suggested to improve efficiency in weak coupling, and suppress voltage gain variation under coil displacement. Power conversion efficiency improvement techniques for rectifier and converter are also proposed. By using the proposed technique for the converter, we can remove the bootstrap capacitors, and reduce the overall size of power circuits. In conclusion, techniques in coil parts and circuit parts to handle challenges in WPT for BIMD are fully investigated in this thesis in addition to the efficiency improvement and control techniques in common WPT. All the techniques are verified through simulations or experiments. The approaches realized in the thesis can be applied to other applications employing the WPT.clos

    A Novel Floating High-Voltage Level Shifter with Pre-Storage Technique

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    This paper proposes a novel floating high-voltage level shifter (FHV-LS) with the pre-storage technique for high speed and low deviation in propagation delay. With this technology, the transmission paths from input to output are optimized, and thus the propagation delay of the proposed FHV-LS is reduced to as low as the sub-nanosecond scale. To further reduce the propagation delay, a pull-up network with regulated strength is introduced to reduce the fall time, which is a crucial part of the propagation delay. In addition, a pseudosymmetrical input pair is used to improve the symmetry of FHV-LS structurally to balance between the rising and falling propagation delays. Moreover, a start-up circuit is developed to initialize the output state of FHV-LS during the VDDH power up. The proposed FHV-LS is implemented using 0.3-”m HVCMOS technology. Post-layout simulation shows that the propagation delays and energy per transition of the proposed FHV-LS are 384 ps and 77.7 pJ @VH = 5 V, respectively. Finally, the 500-points Monte Carlo are performed to verify the performance and the stability

    Reconfigurable Gate Driver Toward High-Power Efficiency and High-Power Density Converters

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    Les systĂšmes de gestion de l'Ă©nergie exigent des convertisseurs de puissance pour fournir une conversion de puissance adaptĂ©e Ă  diverses utilisations. Il existe diffĂ©rents types de convertisseurs de puissance, tel que les amplificateurs de puissance de classe D, les demi-ponts, les ponts complets, les amplificateurs de puissance de classe E, les convertisseurs buck et derniĂšrement les convertisseurs boost. Prenons par exemple les dispositifs implantables, lorsque l'Ă©nergie est prĂ©levĂ©e de la source principale, des convertisseurs de puissance buck ou boost sont nĂ©cessaires pour traiter l'Ă©nergie de l'entrĂ©e et fournir une Ă©nergie propre et adaptĂ©e aux diffĂ©rentes parties du systĂšme. D'autre part, dans les stations de charge des voitures Ă©lectriques, les nouveaux tĂ©lĂ©phones portables, les stimulateurs neuronaux, etc., l'Ă©nergie sans fil a Ă©tĂ© utilisĂ©e pour assurer une alimentation Ă  distance, et des amplificateurs de puissance de classe E sont dĂ©veloppĂ©s pour accomplir cette tĂąche. Les amplificateurs de puissance de classe D sont un excellent choix pour les casques d'Ă©coute ou les haut-parleurs en raison de leur grande efficacitĂ©. Dans le cas des interfaces de capteurs, les demi-ponts et les ponts complets sont les interfaces appropriĂ©es entre les systĂšmes Ă  faible et Ă  forte puissance. Dans les applications automobiles, l'interface du capteur reçoit le signal du cĂŽtĂ© puissance rĂ©duite et le transmet Ă  un rĂ©seau du cĂŽtĂ© puissance Ă©levĂ©e. En outre, l'interface du capteur doit recevoir un signal du cĂŽtĂ© haute puissance et le convertir vers la cĂŽtĂ© basse puissance. Tous les systĂšmes mentionnĂ©s ci-dessus nĂ©cessitent l'inclusion d'un pilote de porte spĂ©cifique dans les circuits, selon les applications. Les commandes de porte comprennent gĂ©nĂ©ralement un dĂ©calage du niveau de commande niveau supĂ©rieur, le levier de changement de niveau infĂ©rieur, une chaĂźne de tampon, un circuit de verrouillage sous tension, un circuit de temps mort, des portes logiques, un inverseur de Schmitt et un mĂ©canisme de dĂ©marrage. Ces circuits sont nĂ©cessaires pour assurer le bon fonctionnement des systĂšmes de conversion de puissance. Un circuit d'attaque de porte reconfigurable prendrait en charge une vaste gamme de convertisseurs de puissance ayant une tension d'entrĂ©e V[indice IN] et un courant de sortie I[indice Load] variables. L'objectif de ce projet est d'Ă©tudier intensivement les causes de diffĂ©rentes pertes dans les convertisseurs de puissance et de proposer ensuite de nouveaux circuits et mĂ©thodologies dans les diffĂ©rents circuits des conducteurs de porte pour atteindre une conversion de puissance avec une haute efficacitĂ© et densitĂ© de puissance. Nous proposons dans cette thĂšse de nouveaux circuits de gestion des temps mort, un Shapeshifter de niveau plus Ă©levĂ© et un Shapeshifter de niveau infĂ©rieur avec de nouvelles topologies qui ont Ă©tĂ© pleinement caractĂ©risĂ©es expĂ©rimentalement. De plus, l'Ă©quation mathĂ©matique du temps mort optimal pour les faces haute et basse d'un convertisseur buck est dĂ©rivĂ©e et expĂ©rimentalement prouvĂ©e. Les circuits intĂ©grĂ©s personnalisĂ©s et les mĂ©thodologies proposĂ©es sont validĂ©s avec diffĂ©rents convertisseurs de puissance, tels que les convertisseurs semi-pont et en boucle ouverte, en utilisant des composants standard pour dĂ©montrer leur supĂ©rioritĂ© sur les solutions traditionnelles. Les principales contributions de cette recherche ont Ă©tĂ© prĂ©sentĂ©es Ă  sept confĂ©rences prestigieuses, trois articles Ă©valuĂ©s par des pairs, qui ont Ă©tĂ© publiĂ©s ou prĂ©sentĂ©s, et une divulgation d'invention. Une contribution importante de ce travail recherche est la proposition d'un nouveau gĂ©nĂ©rateur actif CMOS intĂ©grĂ© dĂ©diĂ© de signaux sans chevauchement. Ce gĂ©nĂ©rateur a Ă©tĂ© fabriquĂ© Ă  l'aide de la technologie AMS de 0.35”m et consomme 16.8mW Ă  partir d'une tension d'alimentation de 3.3V pour commander de maniĂšre appropriĂ©e les cĂŽtĂ©s bas et haut d'un demi-pont afin d'Ă©liminer la propagation. La puce fabriquĂ©e est validĂ©e de façon expĂ©rimentale avec un demi-pont, qui a Ă©tĂ© mis en Ɠuvre avec des composants disponibles sur le marchĂ© et qui contrĂŽle une charge R-L. Les rĂ©sultats des mesures montrent une rĂ©duction de 40% de la perte totale d'un demi-pont de 45V d'entrĂ©e Ă  1MHz par rapport au fonctionnement du demi-pont sans notre circuit intĂ©grĂ© dĂ©diĂ©. Le circuit principal du circuit d'attaque de grille cĂŽtĂ© haut est le dĂ©caleur de niveau, qui fournit un signal de grande amplitude pour le commutateur de puissance cĂŽtĂ© haut. Une nouvelle structure de dĂ©calage de niveau avec un dĂ©lai de propagation minimal doit ĂȘtre prĂ©sentĂ©e. Nous proposons une nouvelle topologie de dĂ©calage de niveau pour le cĂŽtĂ© haut des drivers de porte afin de produire des convertisseurs de puissance efficaces. Le SL prĂ©sente des dĂ©lais de propagation mesurĂ©s de 7.6ns. Les rĂ©sultats mesurĂ©s montrent le fonctionnement du circuit prĂ©sentĂ© sur la plage de frĂ©quence de 1MHz Ă  130MHz. Le circuit fabriquĂ© consomme 31.5pW de puissance statique et 3.4pJ d'Ă©nergie par transition Ă  1kHz, V[indice DDL] = 0.8V , V[indice DDH] = 3.0V, et une charge capacitive C[indice L] = 0.1pF. La consommation Ă©nergĂ©tique totale mesurĂ©e par rapport Ă  la charge capacitive de 0.1 Ă  100nF est indiquĂ©e. Un autre nouveau dĂ©calage vers le bas est proposĂ© pour ĂȘtre utilisĂ© sur le cĂŽtĂ© bas des pilotes de portes. Ce circuit est Ă©galement nĂ©cessaire dans la partie Rₓ du rĂ©seau de bus de donnĂ©es pour recevoir le signal haute tension du rĂ©seau et dĂ©livrer un signal de faible amplitude Ă  la partie basse tension. L'une des principales contributions de ces travaux est la proposition d'un modĂšle de rĂ©fĂ©rence pour l'abaissement de niveau Ă  puissance unique reconfigurable. Le circuit proposĂ© pilote avec succĂšs une gamme de charges capacitives allant de 10fF Ă  350pF. Le circuit prĂ©sentĂ© consomme des puissances statiques et dynamiques de 62.37pW et 108.9”W, respectivement, Ă  partir d'une alimentation de 3.3V lorsqu'il fonctionne Ă  1MHz et pilote une charge capacitive de 10pF. Les rĂ©sultats de la simulation post-layout montrent que les dĂ©lais de propagation de chute et de montĂ©e dans les trois configurations sont respectivement de l'ordre de 0.54 Ă  26.5ns et de 11.2 Ă  117.2ns. La puce occupe une surface de 80”m × 100”m. En effet, les temps morts des cĂŽtĂ©s hauts et bas varient en raison de la diffĂ©rence de fonctionnement des commutateurs de puissance cĂŽtĂ© haut et cĂŽtĂ© bas, qui sont respectivement en commutation dure et douce. Par consĂ©quent, un gĂ©nĂ©rateur de temps mort reconfigurable asymĂ©trique doit ĂȘtre ajoutĂ© aux pilotes de portes traditionnelles pour obtenir une conversion efficace. Notamment, le temps mort asymĂ©trique optimal pour les cĂŽtĂ©s hauts et bas des convertisseurs de puissance Ă  base de Gan doit ĂȘtre fourni par un circuit de commande de grille reconfigurable pour obtenir une conception efficace. Le temps mort optimal pour les convertisseurs de puissance dĂ©pend de la topologie. Une autre contribution importante de ce travail est la dĂ©rivation d'une Ă©quation prĂ©cise du temps mort optimal pour un convertisseur buck. Le gĂ©nĂ©rateur de temps mort asymĂ©trique reconfigurable fabriquĂ© sur mesure est connectĂ© Ă  un convertisseur buck pour valider le fonctionnement du circuit proposĂ© et l'Ă©quation dĂ©rivĂ©e. De plus le rendement d'un convertisseur buck typique avec T[indice DLH] minimum et T[indice DHL] optimal (basĂ© sur l'Ă©quation dĂ©rivĂ©e) Ă  I[indice Load] = 25mA est amĂ©liorĂ© de 12% par rapport Ă  un convertisseur avec un temps mort fixe de T[indice DLH] = T[indice DHL] = 12ns.Power management systems require power converters to provide appropriate power conversion for various purposes. Class D power amplifiers, half and full bridges, class E power amplifiers, buck converters, and boost converters are different types of power converters. Power efficiency and density are two prominent specifications for designing a power converter. For example, in implantable devices, when power is harvested from the main source, buck or boost power converters are required to receive the power from the input and deliver clean power to different parts of the system. In charge stations of electric cars, new cell phones, neural stimulators, and so on, power is transmitted wirelessly, and Class E power amplifiers are developed to accomplish this task. In headphone or speaker driver applications, Class D power amplifiers are an excellent choice due to their great efficiency. In sensor interfaces, half and full bridges are the appropriate interfaces between the low- and high-power sides of systems. In automotive applications, the sensor interface receives the signal from the low-power side and transmits it to a network on the high-power side. In addition, the sensor interface must receive a signal from the high-power side and convert it down to the low-power side. All the above-summarized systems require a particular gate driver to be included in the circuits depending on the applications. The gate drivers generally consist of the level-up shifter, the level-down shifter, a buffer chain, an under-voltage lock-out circuit, a deadtime circuit, logic gates, the Schmitt trigger, and a bootstrap mechanism. These circuits are necessary to achieve the proper functionality of the power converter systems. A reconfigurable gate driver would support a wide range of power converters with variable input voltage V[subscript IN] and output current I[subscript Load]. The goal of this project is to intensively investigate the causes of different losses in power converters and then propose novel circuits and methodologies in the different circuits of gate drivers to achieve power conversion with high-power efficiency and density. We propose novel deadtime circuits, level-up shifter, and level-down shifter with new topologies that were fully characterized experimentally. Furthermore, the mathematical equation for optimum deadtimes for the high and low sides of a buck converter is derived and proven experimentally. The proposed custom integrated circuits and methodologies are validated with different power converters, such as half bridge and open loop buck converters, using off-the-shelf components to demonstrate their superiority over traditional solutions. The main contributions of this research have been presented in seven high prestigious conferences, three peer-reviewed articles, which have been published or submitted, and one invention disclosure. An important contribution of this research work is the proposal of a novel custom integrated CMOS active non-overlapping signal generator, which was fabricated using the 0.35−”m AMS technology and consumes 16.8mW from a 3.3−V supply voltage to appropriately drive the low and high sides of the half bridge to remove the shoot-through. The fabricated chip is validated experimentally with a half bridge, which was implemented with off-the-shelf components and driving a R-L load. Measurement results show a 40% reduction in the total loss of a 45 − V input 1 − MHz half bridge compared with the half bridge operation without our custom integrated circuit. The main circuit of high-side gate driver is the level-up shifter, which provides a signal with a large amplitude for the high-side power switch. A new level shifter structure with minimal propagation delay must be presented. We propose a novel level shifter topology for the high side of gate drivers to produce efficient power converters. The LS shows measured propagation delays of 7.6ns. The measured results demonstrate the operation of the presented circuit over the frequency range of 1MHz to 130MHz. The fabricated circuit consumes 31.5pW of static power and 3.4pJ of energy per transition at 1kHz, V[subscript DDL] = 0.8V , V[subscript DDH] = 3.0V , and capacitive load C[subscript L] = 0.1pF. The measured total power consumption versus the capacitive load from 0.1pF to 100nF is reported. Another new level-down shifter is proposed to be used on the low side of gate drivers. Another new level-down shifter is proposed to be used on the low side of gate drivers. This circuit is also required in the Rₓ part of the data bus network to receive the high-voltage signal from the network and deliver a signal with a low amplitude to the low-voltage part. An essential contribution of this work is the proposal of a single supply reconfigurable level-down shifter. The proposed circuit successfully drives a range of capacitive load from 10fF to 350pF. The presented circuit consumes static and dynamic powers of 62.37pW and 108.9”W, respectively, from a 3.3 − V supply when working at 1MHz and drives a 10pF capacitive load. The post-layout simulation results show that the fall and rise propagation delays in the three configurations are in the range of 0.54 − 26.5ns and 11.2 − 117.2ns, respectively. Its core occupies an area of 80”m × 100”m. Indeed, the deadtimes for the high and low sides vary due to the difference in the operation of the high- and low-side power switches, which are under hard and soft switching, respectively. Therefore, an asymmetric reconfigurable deadtime generator must be added to the traditional gate drivers to achieve efficient conversion. Notably, the optimal asymmetric deadtime for the high and low sides of GaN-based power converters must be provided by a reconfigurable gate driver to achieve efficient design. The optimum deadtime for power converters depends on the topology. Another important contribution of this work is the derivation of an accurate equation of optimum deadtime for a buck converter. The custom fabricated reconfigurable asymmetric deadtime generator is connected to a buck converter to validate the operation of the proposed circuit and the derived equation. The efficiency of a typical buck converter with minimum T[subscript DLH] and optimal T[subscript DHL] (based on the derived equation) at I[subscript Load] = 25mA is improved by 12% compared to a converter with a fixed deadtime of T[subscript DLH] = T[subscript DHL] = 12ns

    Study and design of topologies and components for high power density DC-DC converters

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    Size reduction of low power electronic DC–DC converters is a topic of major interest for power electronics which requires the study and design of circuits and components working under redefined requirements. For this purpose, novel circuital topologies provide advantages in terms of power density increment, especially where a single chip design is feasible. These concepts have been applied to design and implement an integrated high step-down multiphase buck converter and to study the miniaturization of a stackable fiflyback architecture. Particular attention has been dedicated to power inductors, focusing on the modeling and measurement of magnetic materials’ hysteresis and core losses

    Low Power High Efficiency Integrated Class-D Amplifier Circuits for Mobile Devices

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    The consumer’s demand for state-of-the-art multimedia devices such as smart phones and tablet computers has forced manufacturers to provide more system features to compete for a larger portion of the market share. The added features increase the power consumption and heat dissipation of integrated circuits, depleting the battery charge faster. Therefore, low-power high-efficiency circuits, such as the class-D audio amplifier, are needed to reduce heat dissipation and extend battery life in mobile devices. This dissertation focuses on new design techniques to create high performance class-D audio amplifiers that have low power consumption and occupy less space. The first part of this dissertation introduces the research motivation and fundamentals of audio amplification. The loudspeaker’s operation and main audio performance metrics are examined to explain the limitations in the amplification process. Moreover, the operating principle and design procedure of the main class-D amplifier architectures are reviewed to provide the performance tradeoffs involved. The second part of this dissertation presents two new circuit designs to improve the audio performance, power consumption, and efficiency of standard class-D audio amplifiers. The first work proposes a feed-forward power-supply noise cancellation technique for single-ended class-D amplifier architectures to improve the power-supply rejection ratio across the entire audio frequency range. The design methodology, implementation, and tradeoffs of the proposed technique are clearly delineated to demonstrate its simplicity and effectiveness. The second work introduces a new class-D output stage design for piezoelectric speakers. The proposed design uses stacked-cascode thick-oxide CMOS transistors at the output stage that makes possible to handle high voltages in a low voltage standard CMOS technology. The design tradeoffs in efficiency, linearity, and electromagnetic interference are discussed. Finally, the open problems in audio amplification for mobile devices are discussed to delineate the possible future work to improve the performance of class-D amplifiers. For all the presented works, proof-of-concept prototypes are fabricated, and the measured results are used to verify the correct operation of the proposed solutions

    Electronic operation and control of high-intensity gas-discharge lamps

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    The ever increasing amount of global energy consumption based on the application of fossil fuels is threatening the earth’s natural resources and environment. Worldwide, grid-based electric lighting consumes 19 % of total global electricity production. For this reason the transition towards energy efficient lighting plays an important environmental role. One of the key technologies in this transition is High-Intensity Discharge (HID) lighting. The technical revolution in gas-discharge lamps has resulted in the highlyefficient lamps that are available nowadays. As with most energy efficient light solutions, all HID lighting systems require a ballast to operate. Traditionally, magnetic ballast designs were the only choice available for HID lighting systems. Today, electronic lampdrivers can offer additional power saving, flicker free operation, and miniaturisation. Electronic lamp operation enables additional degrees of freedom in lamp-current control over the conventional electro-magnetic (EM) ballasts. The lamp-driver system performance depends on both the dynamics of the lamp and the driver. This thesis focuses on the optimisation of electronically operated HID systems, in terms of highly-efficient lamp-driver topologies and, more specifically, lamp-driver interaction control. First, highly-efficient power topologies to operate compact HID lamps on low-frequency-square-wave (LFSW) current are explored. The proposed two-stage electronic lamp-driver consists of a Power Factor Corrector (PFC) stage that meets the power utility standards. This converter is coupled to a stacked buck converter that controls the lamp-current. Both stages are operated in Zero Voltage Switching (ZVS) mode in order to reduce the switching losses. The resulting two-stage lamp-drivers feature flexible controllability, high efficiency, and high power density, and are suitable for power sandwich packaging. Secondly, lamp-driver interaction (LDI) has been studied in the simulation domain and control algorithms have been explored that improve the stability, and enable system optimisation. Two HID lamp models were developed. The first model describes the HID lamp’s small-signal electrical behaviour and its purpose is to aid to study the interaction stability. The second HID lamp model has been developed based on physics equations for the arc column and the electrode behaviour, and is intended for lampdriver simulations and control applications. Verification measurements have shown that the lamp terminal characteristics are present over a wide power and frequency range. Three LDI control algorithms were explored, using the proposed lampmodels. The first control principle optimises the LDI for a broad range of HID lamps operated at normal or reduced power. This approach consists of two control loops integrated into a fuzzy-logic controller that stabilises the lamp-current and optimises the commutation process. The second control problem concerns the application of ultra high performance (UHP) HID lamps in projection applications that typically set stringent requirements on the quality of the light generated by these lamps, and therefore the lampcurrent. These systems are subject to periodic disturbances synchronous with the LFSW commutation period. Iterative learning control (ILC) has been examined. It was experimentally verified that this algorithm compensates for repetitive disturbances. Third, Electronic HID operation also opens the door for continuous HID lamp dimming that can provide additional savings. To enable stable dimming, an observer-based HID lamp controller has been developed. This controller sets a stable minimum dim-level and monitors the gas-discharge throughout lamp life. The HID lamp observer derives physical lamp state signals from the HID arc discharge physics and the related photometric properties. Finally, practical measurements proved the proposed HID lamp observer-based control principle works satisfactorily

    Architectures and circuits for low-voltage energy conversion and applications in renewable energy and power management

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 337-343).In this thesis we seek to develop smaller, less expensive, and more efficient power electronics. We also investigate emerging applications where the proper implementation of these new types of power converters can have a significant impact on the overall system performance. We have developed a new two-stage dc-dc converter architecture suitable for low-voltage CMOS power delivery. The architecture, which combines the benefits of switched-capacitor and inductor-based converters, achieves both large voltage step-down and high switching frequency, while maintaining good efficiency. We explore the benefits of a new soft-charging technique that drastically reduces the major loss mechanism in switched-capacitor converters, and we show experimental results from a 5-to-1 V, 0.8 W integrated dc-dc converter developed in 180 nm CMOS technology. The use of power electronics to increase system performance in a portable thermophotovoltaic power generator is also investigated in this thesis. We show that mechanical non-idealities in a MEMS fabricated energy conversion device can be mitigated with the help of low-voltage distributed maximum power point tracking (MPPT) dc-dc converters. As part of this work, we explore low power control and sensing architectures, and present experimental results of a 300 mW integrated MPPT developed in 0.35 um CMOS with all power, sensing and control circuitry on chip. The final piece of this thesis investigates the implementation of distributed power electronics in solar photovoltaic applications. We explore the benefits of small, intelligent power converters integrated directly into the solar panel junction box to enhance overall energy capture in real-world scenarios. To this end, we developed a low-cost, high efficiency (>98%) power converter that enables intelligent control and energy conversion at the sub-panel level. Experimental field measurements show that the solution can provide up to a 35% increase in panel output power during partial shading conditions compared to current state-of-the-art solutions.by Robert C. N. Pilawa-Podgurski.Ph.D

    Modeling and control of stand-alone AC microgrids: centralized and distributed storage, energy management and distributed photovoltaic and wind generation

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    El aumento de la penetraciĂłn de energĂ­as renovables en la red elĂ©ctrica es necesario para el desarrollo de un sistema sostenible. Para hacerlo posible tĂ©cnicamente, se ha planteado el uso de microrredes, definidas como una combinaciĂłn de cargas, generadores distribuidos y elementos de almacenamiento controlados gracias a una estrategia global de gestiĂłn energĂ©tica. AdemĂĄs, las microrredes aumentan la fiabilidad del sistema puesto que pueden funcionar en modo aislado en caso de fallo de red. Esta tesis se centra en el desarrollo de microrredes AC en funcionamiento aislado. El objetivo principal es el diseño y la implementaciĂłn de estrategias de gestiĂłn energĂ©ticas sin utilizar cables de comunicaciĂłn entre los distintos elementos, lo que permite reducir los costes del sistema y aumentar su fiabilidad. Para ello, se abordan los siguientes aspectos: ‱ GestiĂłn energĂ©tica de una microrred AC con generador diesel, almacenamiento centralizado y generaciĂłn renovable distribuida ‱ Diseño de tĂ©cnicas de control “droop” para repartir la corriente entre inversores conectados en paralelo ‱ GestiĂłn energĂ©tica de una microrred AC con almacenamiento distribuido y generaciĂłn renovable distribuida ‱ Control de la etapa DC/DC de inversores fotovoltaicos con pequeño condensador de entrada en el seno de una microrred ‱ Control de extracciĂłn de mĂĄxima potencia sin sensores mecĂĄnicos para sistemas minieĂłlicos en el seno de una microrred.The introduction of distributed renewable generators into the electrical grid is required for a sustainable system. In order to increase the penetration of renewable energies, microgrids are usually proposed as one of the most promising technologies. A microgrid is a combination of loads, distributed generators and storage elements which behaves as a single controllable unit for the grid operator. Furthermore, microgrids make it possible to improve the system reliability because they are capable of standalone operation in case of grid failure. This thesis is focused on the development of AC microgrids under stand-alone operation. Its main objective is to design and implement overall control strategies which do not require the use of communication cables, thereby reducing costs and improving reliability. For this purpose, the following aspects are tackled: ‱ Energy management of an AC microgrid with diesel generator, centralized storage and distributed renewable generation ‱ Design of droop methods so that the current is shared among parallel-connected inverters ‱ Energy management of an AC microgrid with distributed storage and distributed renewable generation ‱ Control of the DC/DC stage in photovoltaic inverters with small input capacitors within a microgrid ‱ Sensorless MPPT control for small wind turbines within a microgrid.Programa Oficial de Doctorado en EnergĂ­as Renovables (RD 1393/2007)Energia Berriztagarrietako Doktoretza Programa Ofiziala (ED 1393/2007
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