9,372 research outputs found

    A programmable VLSI filter architecture for application in real-time vision processing systems

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    An architecture is proposed for the realization of real-time edge-extraction filtering operation in an Address-Event-Representation (AER) vision system. Furthermore, the approach is valid for any 2D filtering operation as long as the convolutional kernel F(p,q) is decomposable into an x-axis and a y-axis component, i.e. F(p,q)=H(p)V(q), for some rotated coordinate system [p,q]. If it is possible to find a coordinate system [p,q], rotated with respect to the absolute coordinate system a certain angle, for which the above decomposition is possible, then the proposed architecture is able to perform the filtering operation for any angle we would like the kernel to be rotated. This is achieved by taking advantage of the AER and manipulating the addresses in real time. The proposed architecture, however, requires one approximation: the product operation between the horizontal component H(p) and vertical component V(q) should be able to be approximated by a signed minimum operation without significant performance degradation. It is shown that for edge-extraction applications this filter does not produce performance degradation. The proposed architecture is intended to be used in a complete vision system known as the Boundary-Contour-System and Feature-Contour-System Vision Model, proposed by Grossberg and collaborators. The present paper proposes the architecture, provides a circuit implementation using MOS transistors operated in weak inversion, and shows behavioral simulation results at the system level operation and electrical simulation and experimental results at the circuit level operation of some critical subcircuits

    Automated Synthesis of SEU Tolerant Architectures from OO Descriptions

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    SEU faults are a well-known problem in aerospace environment but recently their relevance grew up also at ground level in commodity applications coupled, in this frame, with strong economic constraints in terms of costs reduction. On the other hand, latest hardware description languages and synthesis tools allow reducing the boundary between software and hardware domains making the high-level descriptions of hardware components very similar to software programs. Moving from these considerations, the present paper analyses the possibility of reusing Software Implemented Hardware Fault Tolerance (SIHFT) techniques, typically exploited in micro-processor based systems, to design SEU tolerant architectures. The main characteristics of SIHFT techniques have been examined as well as how they have to be modified to be compatible with the synthesis flow. A complete environment is provided to automate the design instrumentation using the proposed techniques, and to perform fault injection experiments both at behavioural and gate level. Preliminary results presented in this paper show the effectiveness of the approach in terms of reliability improvement and reduced design effort

    Phishing – the threat of internet banking

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    The attractiveness of Internet banking, the dynamics and the integration with e-business is still growing. The current use of electronic banking is defined by cyberspace and abused in the form of cyber terrorism as well. Therefore it is in the interest of all banks to focus on minimizing the real attacks. This article analyzes and compares the current possibilities against so-called phishing and identifies the area of the safe use of Internet banking in terms of the current potential threats in this area

    Remembering 'zeal' but not 'thing':reverse frequency effects as a consequence of deregulated semantic processing

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    More efficient processing of high frequency (HF) words is a ubiquitous finding in healthy individuals, yet frequency effects are often small or absent in stroke aphasia. We propose that some patients fail to show the expected frequency effect because processing of HF words places strong demands on semantic control and regulation processes, counteracting the usual effect. This may occur because HF words appear in a wide range of linguistic contexts, each associated with distinct semantic information. This theory predicts that in extreme circumstances, patients with impaired semantic control should show an outright reversal of the normal frequency effect. To test this prediction, we tested two patients with impaired semantic control with a delayed repetition task that emphasised activation of semantic representations. By alternating HF and low frequency (LF) trials, we demonstrated a significant repetition advantage for LF words, principally because of perseverative errors in which patients produced the previous LF response in place of the HF target. These errors indicated that HF words were more weakly activated than LF words. We suggest that when presented with no contextual information, patients generate a weak and unstable pattern of semantic activation for HF words because information relating to many possible contexts and interpretations is activated. In contrast, LF words tend are associated with more stable patterns of activation because similar semantic information is activated whenever they are encountered

    Are IEEE 1500 compliant cores really compliant to the standard?

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    Functional verification of complex SoC designs is a challenging task, which fortunately is increasingly supported by automation. This article proposes a verification component for IEEE Std 1500, to be plugged into a commercial verification tool suit

    Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

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    Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

    Elaboration versus suppression of cued memories: influence of memory recall instruction and success on parietal lobe, default network, and hippocampal activity.

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    Functional imaging studies of episodic memory retrieval consistently report task-evoked and memory-related activity in the medial temporal lobe, default network and parietal lobe subregions. Associated components of memory retrieval, such as attention-shifts, search, retrieval success, and post-retrieval processing also influence regional activity, but these influences remain ill-defined. To better understand how top-down control affects the neural bases of memory retrieval, we examined how regional activity responses were modulated by task goals during recall success or failure. Specifically, activity was examined during memory suppression, recall, and elaborative recall of paired-associates. Parietal lobe was subdivided into dorsal (BA 7), posterior ventral (BA 39), and anterior ventral (BA 40) regions, which were investigated separately to examine hypothesized distinctions in sub-regional functional responses related to differential attention-to-memory and memory strength. Top-down suppression of recall abolished memory strength effects in BA 39, which showed a task-negative response, and BA 40, which showed a task-positive response. The task-negative response in default network showed greater negatively-deflected signal for forgotten pairs when task goals required recall. Hippocampal activity was task-positive and was influenced by memory strength only when task goals required recall. As in previous studies, we show a memory strength effect in parietal lobe and hippocampus, but we show that this effect is top-down controlled and sensitive to whether the subject is trying to suppress or retrieve a memory. These regions are all implicated in memory recall, but their individual activity patterns show distinct memory-strength-related responses when task goals are varied. In parietal lobe, default network, and hippocampus, top-down control can override the commonly identified effects of memory strength
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