Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Thermo-mechanical stress measurement and analysis in three dimensional interconnect structures

Three-dimensional (3-D) integration is effective to overcome the wiring limit imposed on device density and performance with continued scaling. The application of TSV (Through-Silicon Via) is essential for 3D IC integration. TSVs are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. However, due to the large CTE mismatch between Silicon and Copper, thermal stresses are induced by various thermal histories from the device processing, and they have caused serious concerns regarding the thermal-mechanical reliability. Firstly, a semi-analytic approach is introduced to understand stress distributions in TSV structures. This is followed by application of finite element analysis for more accurate prediction of stress behavior according to the real geometry of the sample. The conventional Raman method is used to measure the linear combination of in-plane stress components near silicon top surface Secondly, the limitation of conventional Raman method is discussed: only certain linear combination of in-plane stress, instead of separate value for each stress components, can be obtained. Two different kinds of innovative Raman measurements have been developed and employed to study the normal stress components separately. Both of them take advantages of different laser polarization profiles to resolve the normal stress components separately based on experimental data. The top-down Raman measurements utilize so called “high NA effect” to obtain additional information, and can resolve all 3 normal stress components. Independent bending beam experiments are used to validate the results from cross-section Raman measurement on the same sample. The correlation between top-down Raman measurement and cross-section Raman measurement are investigated as well. Lastly, as a typical example of 3D IC package, a stack-die memory package is presented. Finite element analysis combined with cross-section Raman measurement and high resolution moiré interferometry were employed to investigate the thermal-mechanical reliability and chip-package interaction of the stack-die memory structure.Physic

Carbon Nanotube Interconnects for End-of-Roadmap Semiconductor Technology Nodes

Advances in semiconductor technology due to aggressive downward scaling of on-chip feature sizes have led to rapid rises in resistivity and current density of interconnect conductors. As a result, current interconnect materials, Cu and W, are subject to performance and reliability constraints approaching or exceeding their physical limits. Therefore, alternative materials such as nanocarbons, metal silicides, and Ag nanowires are actively considered as potential replacements to meet such constraints. Among nanocarbons, carbon nanotube (CNT) is among the leading replacement candidate for on-chip interconnect vias due to its high aspect-ratio nanostructure and superior currentcarrying capacity to those of Cu, W, and other potential candidates. However, contact resistance of CNT with metal is a major bottleneck in device functionalization. To meet the challenge posed by contact resistance, several techniques are designed and implemented. First, the via fabrication and CNT growth processes are developed to increase the CNT packing density inside via and to ensure no CNT growth on via sidewalls. CNT vias with cross-sections down to 40 nm 40 nm are fabricated, which have linewidths similar to those used for on-chip interconnects in current integrated circuit manufacturing technology nodes. Then the via top contact is metallized to increase the total CNT area interfacing with the contact metal and to improve the contact quality and reproducibility. Current-voltage characteristics of individual fabricated CNT vias are measured using a nanoprober and contact resistance is extracted with a first-reported contact resistance extraction scheme for 40 nm linewidth. Based on results for 40 nm and 60 nm top-contact metallized CNT vias, we demonstrate that not only are their current-carrying capacities two orders of magnitude higher than their Cu and W counterparts, they are enhanced by reduced via resistance due to contact engineering. While the current-carrying capacities well exceed those projected for end-of-roadmap technology nodes, the via resistances remain a challenge to replace Cu and W, though our results suggest that further innovations in contact engineering could begin to overcome such challenge

Investigation into yield and reliability enhancement of TSV-based three-dimensional integration circuits

Three dimensional integrated circuits (3D ICs) have been acknowledged as a promising technology to overcome the interconnect delay bottleneck brought by continuous CMOS scaling. Recent research shows that through-silicon-vias (TSVs), which act as vertical links between layers, pose yield and reliability challenges for 3D design. This thesis presents three original contributions.The first contribution presents a grouping-based technique to improve the yield of 3D ICs under manufacturing TSV defects, where regular and redundant TSVs are partitioned into groups. In each group, signals can select good TSVs using rerouting multiplexers avoiding defective TSVs. Grouping ratio (regular to redundant TSVs in one group) has an impact on yield and hardware overhead. Mathematical probabilistic models are presented for yield analysis under the influence of independent and clustering defect distributions. Simulation results using MATLAB show that for a given number of TSVs and TSV failure rate, careful selection of grouping ratio results in achieving 100% yield at minimal hardware cost (number of multiplexers and redundant TSVs) in comparison to a design that does not exploit TSV grouping ratios. The second contribution presents an efficient online fault tolerance technique based on redundant TSVs, to detect TSV manufacturing defects and address thermal-induced reliability issue. The proposed technique accounts for both fault detection and recovery in the presence of three TSV defects: voids, delamination between TSV and landing pad, and TSV short-to-substrate. Simulations using HSPICE and ModelSim are carried out to validate fault detection and recovery. Results show that regular and redundant TSVs can be divided into groups to minimise area overhead without affecting the fault tolerance capability of the technique. Synthesis results using 130-nm design library show that 100% repair capability can be achieved with low area overhead (4% for the best case). The last contribution proposes a technique with joint consideration of temperature mitigation and fault tolerance without introducing additional redundant TSVs. This is achieved by reusing spare TSVs that are frequently deployed for improving yield and reliability in 3D ICs. The proposed technique consists of two steps: TSV determination step, which is for achieving optimal partition between regular and spare TSVs into groups; The second step is TSV placement, where temperature mitigation is targeted while optimizing total wirelength and routing difference. Simulation results show that using the proposed technique, 100% repair capability is achieved across all (five) benchmarks with an average temperature reduction of 75.2? (34.1%) (best case is 99.8? (58.5%)), while increasing wirelength by a small amount

Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics

The fundamental motivation for this dissertation is to address the widening interconnect gap between integrated circuit (IC) demands and package substrates specifically for high frequency digital-RF systems applications. Moore's law for CMOS ICs predicts that transistor density on ICs will double approximately every 18 months. The current state-of-the-art in IC package substrates is at 20µm lines/spaces and 50-60µm microvia diameter using epoxy dielectrics with loss tangent above 0.01. The research targets are to overcome the barriers of current technologies and demonstrate a set of advanced materials and process technologies capable of 5-10µm lines and spaces, and 10-30µm diameter microvias in a multilayer 3-D wiring substrate using 10-25µm thin film dielectrics with loss tangent in the <0.005. The research elements are organized as follows with a clear focus on understanding and characterization of fundamental materials structure-processing-property relationships and interfaces to achieve the next generation targets. (a) Low CTE Core Substrate, (b) Low Loss Dielectrics with 25µm and smaller microvias, (c) Sub-10µm Width Cu Conductors, and (d) Integration of the various dielectric and conductor processes.Ph.D.Committee Chair: Tummala, Rao; Committee Member: Iyer, Mahadevan; Committee Member: Saxena, Ashok; Committee Member: Swaminathan, Madhavan; Committee Member: Wong, Chingpin

Novel Photostructurable Polymer for On-Board Optical Interconnects Enabled by Femtosecond Direct Laser Writing

Die integrierte Optik hat sich als vielversprechende Lösung für elektronische Verbindungen erwiesen, die eine hohe Bandbreitendichte und einen geringen Stromverbrauch ermöglicht. Seit kurzem ist es möglich photochemische und physikalische Reaktionen auf ein Mikrovolumen zu begrenzen. Dies hat der optischen Verbindungstechnik unter Verwendung von Glas oder Polymer eine zusätzliche Dimension verliehen. Dreidimensionale Wellenleiter können das optische Signal zwischen Blöcken aller Dimensionen verbinden, kombinieren oder aufteilen. Die Erhöhung des Brechungsindex ist jedoch immer noch eine Herausforderung für die Herstellung stabiler Freiform- und monomodaler Wellenleiter mit dreidimensionaler Ausdehnung, welche sich innerhalb der Platine befinden. Diese Dissertation stellt ein neues Konzept vor, um dieser Herausforderung zu begegnen, indem direktes Femtosekunden-Laserschreiben in Polymer und externe Diffusion eines gasförmigen Monomers verwendet wird. Direktes Laserschreiben mit Zwei-Photonen-Absorption wurde verwendet, um die Vernetzung entlang eines vorher definierten Pfades zur Bildung des Wellenleiterkerns zu initiieren. Es wurde ein ausreichender Brechungsindexkontrast erzeugt, um gaußförmige Strahlen mit einem Modus zu führen. Feature-Größen konnten durch Variieren der Scangeschwindigkeit und der Laserintensität linear angepasst werden. Dieses Herstellungsverfahren erfordert nur eine Schicht eines einzelnen Materials ohne Masken-, Kontakt- oder Nassbearbeitung. Durch Verwendung dieser neuartigen Methode wurden dreidimensionale optische Wellenleiter-Arrays, Fan-in/Fan-out- und Splitter-Strukturen hergestellt. Dreidimensionale freiforme Wellenleiter haben ein hohes Potential zur Verbesserung der Packungsdichte und Flexibilität optischer Verbindungen auf Platinenebene

High-frequency characterization of embedded components in printed circuit boards

The embedding of electronic components is a three-dimensional packaging technology, where chips are placed inside of the printed circuit board instead of on top. The advantage of this technology is the reduced electronic interconnection length between components. The shorter this connection, the faster the signal transmission can occur. Different high-frequency aspects of chip embedding are investigated within this dissertation: interconnections to the embedded chip, crosstalk between signals on the chip and on the board, and interconnections running on top of or underneath embedded components. The high-frequency behavior of tracks running near embedded components is described using a broadband model for multilayer microstrip transmission lines. The proposed model can be used to predict the characteristic impedance and the loss of the lines. The model is based on two similar approximations that reduce the multilayer substrate to an equivalent single-layer structure. The per-unit-length shunt impedance parameters are derived from the complex effective dielectric constant, which is obtained using a variational method. A complex image approach results in the calculation of a frequency-dependent effective height that can be used to determine the per-unit-length resistance and inductance. A deliberate choice was made for a simple but accurate model that could easily be implemented in current high-frequency circuit simulators. Next to quasi-static electromagnetic simulations, a dedicated test vehicle that allows for the direct extraction of the propagation constant of these multilayer microstrips is manufactured and used to verify the model. The verification of the model using simulation and measurements shows that the proposed model slightly overestimates the loss of the measured multilayer microstrips, but is more accurate than the simulations in predicting the characteristic impedance

Copper wafer bonding in three-dimensional integration

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 165-176).Three-dimensional (3D) integration, in which multiple layers of devices are stacked with high density of interconnects between the layers, offers solutions for problems when the critical dimensions in integrated circuits keep shrinking. Copper wafer bonding has been considered as a strong candidate for fabrication of three-dimensional integrated circuits (3-D IC). This thesis work involves fundamental studies of copper wafer bonding and bonding performance of bonded interconnects. Copper bonded wafers exhibit good bonding qualities and present no original bonding interfaces when the bonding process occurs at 400⁰C/4000 mbar for 30 min, followed by nitrogen anneal at 400⁰C for 30 min. Oxide distribution in the bonded layer is uniform and sparse. Evolution of microstructure morphologies and grain orientations of copper bonded wafers during bonding and annealing were studied. The bonded layer reaches steady state after post-bonding anneal. The microstructure morphologies and bond strengths of copper bonded wafers under different bonding conditions were investigated.A map summarizing these results provides a useful reference on process conditions suitable for three-dimensional integration based on copper wafer bonding. Similar microstructure morphology of copper bonded interconnects was observed to that of copper bonded wafers. Specific contact resistances of bonded interconnects of approximately 10⁻⁸ [ohms]-cm² were measured by using a novel test structure which can eliminate the errors from misalignment during bonding. The bonding qualities of different interconnect sizes and densities have been investigated. In addition to increasing the bonding temperature and duration, options such as larger interconnect sizes, total bonding area, or use of dummy pads for bonding in the unused area improve the quality of bonded interconnects. Process development of silicon layer stacking based on Cu wafer bonding was successfully applied to demonstrate a strong four-layer-stack structure.Bonded Cu layers in this structure become homogeneous layers and do not show original bonding interfaces. This process can be reliably applied in three-dimensional integration applications.by Kuan-Neng Chen.Ph.D

Interfacial fracture of micro thin film interconnects under monotonic and cyclic loading

The goal of this research was to develop new experimental techniques to quantitatively study the interfacial fracture of micro-contact thin film interconnects used in microelectronic applications under monotonic and cyclic loadings. The micro-contact spring is a new technology that is based on physical vapor deposited thin film cantilevers with a purposely-imposed stress gradient through the thickness of the film. These "springs" have the promise of being the solution to address near-term wafer level probing and long-term high-density chip-to-next level microelectronic packaging challenges, as outlined by the International Technology Roadmap for Semiconductors. The success of this technology is, in part, dependent on the ability to understand the failure mechanism under monotonic and cyclic loadings. This research proposes two experimental methods to understand the interfacial fracture under such monotonic and fatigue loading conditions. To understand interfacial fracture under monotonic loading, a fixtureless superlayer-based delamination test has been developed. Using stress-engineered Cr layer and a release layer with varying width, this test can be used to measure interfacial fracture toughness under a wide range of mode mixity. This test uses common IC fabrication techniques and overcomes the shortcomings of available methods. The developed test has been used to measure the interfacial fracture toughness for Ti/Si interface. It was found that for low mode mixity Ti/Si thin film interfaces, the fracture toughness approaches the work of adhesion which is essentially the Ti-Si bond energy for a given bond density. In addition to the monotonic decohesion test, a fixtureless fatigue test is developed to investigate the interfacial crack propagation. Using a ferromagnetic material deposited on the micro-contact spring, this test employs an external magnetic field to be able to drive the interfacial crack. Fatigue crack growth can be monitored by E-beam lithography patterned metal traces that are 10 to 40nm wide and 1 to a few µm in spacing. The crack initiation and propagation can be monitored through electrical resistance measurement. In the conducted experiments, it is seen that the interfacial delamination does not occur under fatigue loading, and that the micro-contact springs are robust against interfacial fracture for probing and packaging applications.Ph.D.Committee Chair: Sitaraman, Suresh; Committee Member: Degertekin,Levent; Committee Member: McDowell, David; Committee Member: Tummala,Rao; Committee Member: Vandentop, Gilroy; Committee Member: Wang, Zhong Li