High Frequency Multiferroic Devices

This dissertation focuses on high frequency multiferroic devices from both theoretical and experimental aspects. Some potential applications for high frequency multiferroic: antennas, logic and memory, will be presented in this dissertation. The introduction section provides a fundamental explanation on the multiferroic devices as well as the modeling methods for strain-mediated multiferroic systems. Former researches indicate that the composites of piezoelectric substrate and the magnetoelastic material show great potential on reducing both the devices’ size as well as energy consumption.Part I of the dissertation shows multiferroics for antenna applications. Conventionally, antennas such as dipoles and loops rely on an electromagnetic (EM) wave resonance. Therefore, the sizes of such antennas are within the same order of free space wavelength. Multiferroic antenna can transfer the EM wave into an acoustic wave, which has much smaller wavelength compared with the wavelength of the EM wave under the same frequency. In this way, multiferroic antennas show a promising path for reducing the antenna system’s size, weight and volume. Also, three multiferroic antennas: shear wave antenna, lamb wave antenna as well as tunable frequency broadband antenna are introduced in this section. The shear wave antenna and lamb wave antenna are studied experimentally, and the tunable frequency broadband antenna is studied theoretically. All of them show great potential on reducing the antenna’s size.Part II of this dissertation indicates other applications of multiferroic devices: logic and memory. For the logic aspects, a numerical simulation is performed on in-plane mode Bennett clocking systems. For memory aspects, a new concept for breaking the switch symmetry the high frequency control of the magnetization in nanodisk. In this part, a fully coupled finite element model is used to simulate the switch process of the magnetization in the nanodisks. This voltage-controlled process has potential be used in magnetic memory devices with very low energy dissipations

BOOLEAN AND BRAIN-INSPIRED COMPUTING USING SPIN-TRANSFER TORQUE DEVICES

Several completely new approaches (such as spintronic, carbon nanotube, graphene, TFETs, etc.) to information processing and data storage technologies are emerging to address the time frame beyond current Complementary Metal-Oxide-Semiconductor (CMOS) roadmap. The high speed magnetization switching of a nano-magnet due to current induced spin-transfer torque (STT) have been demonstrated in recent experiments. Such STT devices can be explored in compact, low power memory and logic design. In order to truly leverage STT devices based computing, researchers require a re-think of circuit, architecture, and computing model, since the STT devices are unlikely to be drop-in replacements for CMOS. The potential of STT devices based computing will be best realized by considering new computing models that are inherently suited to the characteristics of STT devices, and new applications that are enabled by their unique capabilities, thereby attaining performance that CMOS cannot achieve. The goal of this research is to conduct synergistic exploration in architecture, circuit and device levels for Boolean and brain-inspired computing using nanoscale STT devices. Specifically, we first show that the non-volatile STT devices can be used in designing configurable Boolean logic blocks. We propose a spin-memristor threshold logic (SMTL) gate design, where memristive cross-bar array is used to perform current mode summation of binary inputs and the low power current mode spintronic threshold device carries out the energy efficient threshold operation. Next, for brain-inspired computing, we have exploited different spin-transfer torque device structures that can implement the hard-limiting and soft-limiting artificial neuron transfer functions respectively. We apply such STT based neuron (or ‘spin-neuron’) in various neural network architectures, such as hierarchical temporal memory and feed-forward neural network, for performing “human-like” cognitive computing, which show more than two orders of lower energy consumption compared to state of the art CMOS implementation. Finally, we show the dynamics of injection locked Spin Hall Effect Spin-Torque Oscillator (SHE-STO) cluster can be exploited as a robust multi-dimensional distance metric for associative computing, image/ video analysis, etc. Our simulation results show that the proposed system architecture with injection locked SHE-STOs and the associated CMOS interface circuits can be suitable for robust and energy efficient associative computing and pattern matching

Energy efficient hybrid computing systems using spin devices

Emerging spin-devices like magnetic tunnel junctions (MTJ\u27s), spin-valves and domain wall magnets (DWM) have opened new avenues for spin-based logic design. This work explored potential computing applications which can exploit such devices for higher energy-efficiency and performance. The proposed applications involve hybrid design schemes, where charge-based devices supplement the spin-devices, to gain large benefits at the system level. As an example, lateral spin valves (LSV) involve switching of nanomagnets using spin-polarized current injection through a metallic channel such as Cu. Such spin-torque based devices possess several interesting properties that can be exploited for ultra-low power computation. Analog characteristic of spin current facilitate non-Boolean computation like majority evaluation that can be used to model a neuron. The magneto-metallic neurons can operate at ultra-low terminal voltage of ∼20mV, thereby resulting in small computation power. Moreover, since nano-magnets inherently act as memory elements, these devices can facilitate integration of logic and memory in interesting ways. The spin based neurons can be integrated with CMOS and other emerging devices leading to different classes of neuromorphic/non-Von-Neumann architectures. The spin-based designs involve `mixed-mode\u27 processing and hence can provide very compact and ultra-low energy solutions for complex computation blocks, both digital as well as analog. Such low-power, hybrid designs can be suitable for various data processing applications like cognitive computing, associative memory, and currentmode on-chip global interconnects. Simulation results for these applications based on device-circuit co-simulation framework predict more than ∼100x improvement in computation energy as compared to state of the art CMOS design, for optimal spin-device parameters

Provably Trustworthy and Secure Hardware Design with Low Overhead

Due to the globalization of IC design in the semiconductor industry and outsourcing of chip manufacturing, 3PIPs become vulnerable to IP piracy, reverse engineering, counterfeit IC, and hardware Trojans. To thwart such attacks, ICs can be protected using logic encryption techniques. However, strong resilient techniques incur significant overheads. SCAs further complicate matters by introducing potential attacks post-fabrication. One of the most severe SCAs is PA attacks, in which an attacker can observe the power variations of the device and analyze them to extract the secret key. PA attacks can be mitigated via adding large extra hardware; however, the overheads of such solutions can render them impractical, especially when there are power and area constraints. In our first approach, we present two techniques to prevent normal attacks. The first one is based on inserting MUX equal to half/full of the output bit number. In the second technique, we first design PLGs using SiNW FETs and then replace some logic gates in the original design with their SiNW FETs-based PLGs counterparts. In our second approach, we use SiNW FETs to produce obfuscated ICs that are resistant to advanced reverse engineering attacks. Our method is based on designing a small block, whose output is untraceable, namely URSAT. Since URSAT may not offer very strong resilience against the combined AppSAT-removal attack, S-URSAT is achieved using only CMOS-logic gates, and this increases the security level of the design to robustly thwart all existing attacks. In our third topic, we present the usage of ASLD to produce secure and resilient circuits that withstand IC attacks (during the fabrication) and PA attacks (after fabrication). First, we show that ASLD has unique features that can be used to prevent PA and IC attacks. In our three topics, we evaluate each design based on performance overheads and security guarantees

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within

Understanding Quantum Technologies 2022

Understanding Quantum Technologies 2022 is a creative-commons ebook that provides a unique 360 degrees overview of quantum technologies from science and technology to geopolitical and societal issues. It covers quantum physics history, quantum physics 101, gate-based quantum computing, quantum computing engineering (including quantum error corrections and quantum computing energetics), quantum computing hardware (all qubit types, including quantum annealing and quantum simulation paradigms, history, science, research, implementation and vendors), quantum enabling technologies (cryogenics, control electronics, photonics, components fabs, raw materials), quantum computing algorithms, software development tools and use cases, unconventional computing (potential alternatives to quantum and classical computing), quantum telecommunications and cryptography, quantum sensing, quantum technologies around the world, quantum technologies societal impact and even quantum fake sciences. The main audience are computer science engineers, developers and IT specialists as well as quantum scientists and students who want to acquire a global view of how quantum technologies work, and particularly quantum computing. This version is an extensive update to the 2021 edition published in October 2021.Comment: 1132 pages, 920 figures, Letter forma

Dichotomic role of NAADP/two-pore channel 2/Ca2+ signaling in regulating neural differentiation of mouse embryonic stem cells

Poster Presentation - Stem Cells and Pluripotency: abstract no. 1866The mobilization of intracellular Ca2+stores is involved in diverse cellular functions, including cell proliferation and differentiation. At least three endogenous Ca2+mobilizing messengers have been identified, including inositol trisphosphate (IP3), cyclic adenosine diphosphoribose (cADPR), and nicotinic adenine acid dinucleotide phosphate (NAADP). Similar to IP3, NAADP can mobilize calcium release in a wide variety of cell types and species, from plants to animals. Moreover, it has been previously shown that NAADP but not IP3-mediated Ca2+increases can potently induce neuronal differentiation in PC12 cells. Recently, two pore channels (TPCs) have been identified as a novel family of NAADP-gated calcium release channels in endolysosome. Therefore, it is of great interest to examine the role of TPC2 in the neural differentiation of mouse ES cells. We found that the expression of TPC2 is markedly decreased during the initial ES cell entry into neural progenitors, and the levels of TPC2 gradually rebound during the late stages of neurogenesis. Correspondingly, perturbing the NAADP signaling by TPC2 knockdown accelerates mouse ES cell differentiation into neural progenitors but inhibits these neural progenitors from committing to the final neural lineage. Interestingly, TPC2 knockdown has no effect on the differentiation of astrocytes and oligodendrocytes of mouse ES cells. Overexpression of TPC2, on the other hand, inhibits mouse ES cell from entering the neural lineage. Taken together, our data indicate that the NAADP/TPC2-mediated Ca2+signaling pathway plays a temporal and dichotomic role in modulating the neural lineage entry of ES cells; in that NAADP signaling antagonizes ES cell entry to early neural progenitors, but promotes late neural differentiation.postprin