Paper Session I-B - Development and Operational Applications of a Real-time Range Data Simulator

Whenever a rocket is launched at any U .S. Space Launch Range, safety systems are in place to ensure that human life, health, and property are protected. These range safety systems rely on accurate knowledge of where flight vehicle debris would land in the event of a mishap. They must precisely process and display data from the rocket and ground sensors, and not react in an unpredictable manner to non-nominal or erroneous data. ENSCO has developed the Real-time Instrumentation Simulation Environment (RISE) to evaluate and operationally certify real-time range safety critical systems at space launch facilities. Various RISE configurations thoroughly test range safety critical systems by simulating, injecting, and recording up to 40 simultaneous real-time links of nominal and non-nominal vehicle tracking data, including ground sensor outputs and full-rate telemetry data. RISE simulators include options for the introduction of noise, data dropouts, quality defects, divergent trajectories, single or multiple source latencies, and numerous other data perturbations. By overlaying current timing in the data stream and computing and inserting checksums in real-time, RISE data is indistinguishable from operational mission data. With RISE, launch ranges have the ability to simulate a complete vehicle launch for both nominal and non-nominal conditions. Tests can be ·carefully controlled to validate range safety display systems, identify defects, or support training of operations personnel

FPGA ARCHITECTURE AND VERIFICATION OF BUILT IN SELF-TEST (BIST) FOR 32-BIT ADDER/SUBTRACTER USING DE0-NANO FPGA AND ANALOG DISCOVERY 2 HARDWARE

The integrated circuit (IC) is an integral part of everyday modern technology, and its application is very attractive to hardware and software design engineers because of its versatility, integration, power consumption, cost, and board area reduction. IC is available in various types such as Field Programming Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), System on Chip (SoC) architecture, Digital Signal Processing (DSP), microcontrollers (μC), and many more. With technology demand focused on faster, low power consumption, efficient IC application, design engineers are facing tremendous challenges in developing and testing integrated circuits that guaranty functionality, high fault coverage, and reliability as the transistor technology is shrinking to the point where manufacturing defects of ICs are affecting yield which associates with the increased cost of the part. The competitive IC market is pressuring manufactures of ICs to develop and market IC in a relatively quick turnaround which in return requires design and verification engineers to develop an integrated self-test structure that would ensure fault-free and the quality product is delivered on the market. 70-80% of IC design is spent on verification and testing to ensure high quality and reliability for the enduser. To test complex and sophisticated IC designs, the verification engineers must produce laborious and costly test fixtures which affect the cost of the part on the competitive market. To avoid increasing the part cost due to yield and test time to the end-user and to keep up with the competitive market many IC design engineers are deviating from complex external test fixture approach and are focusing on integrating Built-in Self-Test (BIST) or Design for Test (DFT) techniques onto IC’s which would reduce time to market but still guarantee high coverage for the product. Understanding the BIST, the architecture, as well as the application of IC, must be understood before developing IC. The architecture of FPGA is elaborated in this paper followed by several BIST techniques and applications of those BIST relative to FPGA, SoC, analog to digital (ADC), or digital to analog converters (DAC) that are integrated on IC. Paper is concluded with verification of BIST for the 32-bit adder/subtracter designed in Quartus II software using the Analog Discovery 2 module as stimulus and DE0-NANO FPGA board for verification

A flexible experimental laboratory for distributed generation networks based on power inverters

In the recently deregulated electricity market, distributed generation based on renewable sources is becoming more and more relevant. In this area, two main distributed scenarios are focusing the attention of recent research: grid-connected mode, where the generation sources are connected to a grid mainly supplied by big power plants, and islanded mode, where the distributed sources, energy storage devices, and loads compose an autonomous entity that in its general form can be named a microgrid. To conduct a successful research in these two scenarios, it is essential to have a flexible experimental setup. This work deals with the description of a real laboratory setup composed of four nodes that can emulate both scenarios of a distributed generation network. A comprehensive description of the hardware and software setup will be done, focusing especially in the dual-core DSP used for control purposes, which is next to the industry standards and able to emulate real complexities. A complete experimental section will show the main features of the system.Peer ReviewedPostprint (published version

Prediction of soft error response of integrated circuits to electrostatic discharge injection via simulation field; Package interaction for electrostatic discharge soft error prediction; Full wave model for simulating noise ken electrostatic discharge generator

In the first section, a concept for analyzing soft error response in ICs to ESD via coupling through flex cable structures is presented. Its novelty lies in accounting for the transient electromagnetic fields radiated by the ESD generator that couples to the flex cable PCB thereby causing disturbance on the IC under test. This is accomplished in three stages; first by developing a full wave model of the DUT which includes modeling the PCB and flex cable geometry and validating it in frequency domain with regard to the transfer impedance. This followed by combining the ESD generator with the DUT model to simulate the voltage at the IC input in time domain. Finally the time domain results from full wave simulation are combined with an equivalent IC response model in SPICE to predict soft error failures due ESD. In the second section, a more detailed modeling of the IC including the lead frame geometry, bond wires and IBIS/ICEM models are incorporated to investigate coupling of fields from three different injection techniques - H field loop probes, TEM cell and ESD generator. For the first time a complete simulation model which includes the ESD generator, passive elements of the DUT structure (PCB) and a detailed model of the IC has been developed to predict interaction of radiated field from the generator to the IC. The third section shows a CST MWS model was generated to simulate the discharge current and the transient field of an ESD generator. Individual components of the Noise Ken ESD generator (ESS-2000) were modeled, validated and combined. The complete full wave model was verified by comparing the simulated discharge current waveforms and induced loop voltages with the measured results --Abstract, page iii

Gas Turbines and Associated Auxiliary Systems in Oil and Gas Applications

TutorialThis tutorial elaborates on the various gas turbine auxiliary systems; for mechanical drive applications in oil and gas projects, from an EPC contractor perspective. The tutorial briefly introduces the basics of gas turbines including thermodynamics, types, arrangements, components and combustion technologies. However, the focus of this tutorial remains on the gas turbine auxiliaries where the functions and technology selection options are explained; furthermore, the relevance on the gas turbine performance and availability and the technical constraints for implementation are described. This tutorial contributes; in addition to what have been previously published, by being focused on the engineering of interfaces between the gas turbine, its auxiliary systems, and the plant in oil and gas onshore and offshore projects

An Overview of Applications of the Modular Multilevel Matrix Converter

The modular multilevel matrix converter is a relatively new power converter topology suitable for high-power alternating current (AC)-to-AC applications. Several publications in the literature have highlighted the converter capabilities, such as full modularity, fault-redundancy, control flexibility and input/output power quality. However, the topology and control of this converter are relatively complex to realise, considering that the converter has a large number of power-cells and floating capacitors. To the best of the authors’ knowledge, there are no review papers where the applications of the modular multilevel matrix converter are discussed. Hence, this paper aims to provide a comprehensive review of the state-of-the-art of the modular multilevel matrix converter, focusing on implementation issues and applications. Guidelines to dimensioning the key components of this converter are described and compared to other modular multilevel topologies, highlighting the versatility and controllability of the converter in high-power applications. Additionally, the most popular applications for the modular multilevel matrix converter, such as wind turbines, grid connection and motor drives, are discussed based on analyses of simulation and experimental results. Finally, future trends and new opportunities for the use of the modular multilevel matrix converter in high-power AC-to-AC applications are identified.Agencia Nacional de Investigación y Desarrollo/[Fondecyt 11191163]/ANID/ChileAgencia Nacional de Investigación y Desarrollo/[Fondecyt 1180879]/ANID/ChileAgencia Nacional de Investigación y Desarrollo/[Fondecyt 11190852]/ANID/ChileAgencia Nacional de Investigación y Desarrollo/[ANID Basal FB0008]/ANID/ChileAgencia Nacional de Investigación y Desarrollo/[Fondef ID19I10370]/ANID/ChileUniversidad de Santiago/[Dicyt 091813DD]//ChileUCR::Vicerrectoría de Docencia::Ingeniería::Facultad de Ingeniería::Escuela de Ingeniería Eléctric

Dynamic software randomisation: Lessons learnec from an aerospace case study

Timing Validation and Verification (V&V) is an important step in real-time system design, in which a system's timing behaviour is assessed via Worst Case Execution Time (WCET) estimation and scheduling analysis. For WCET estimation, measurement-based timing analysis (MBTA) techniques are widely-used and well-established in industrial environments. However, the advent of complex processors makes it more difficult for the user to provide evidence that the software is tested under stress conditions representative of those at system operation. Measurement-Based Probabilistic Timing Analysis (MBPTA) is a variant of MBTA followed by the PROXIMA European Project that facilitates formulating this representativeness argument. MBPTA requires certain properties to be applicable, which can be obtained by selectively injecting randomisation in platform's timing behaviour via hardware or software means. In this paper, we assess the effectiveness of the PROXIMA's dynamic software randomisation (DSR) with a space industrial case study executed on a real unmodified hardware platform and an industrial operating system. We present the challenges faced in its development, in order to achieve MBPTA compliance and the lessons learned from this process. Our results, obtained using a commercial timing analysis tool, indicate that DSR does not impact the average performance of the application, while it enables the use of MBPTA. This results in tighter pWCET estimates compared to current industrial practice.The research leading to these results has received funding from the European Community’s FP7 [FP7/2007-2013] under the PROXIMA Project (www.proxima-project.eu), grant agreement no 611085. This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant TIN2015-65316-P and the HiPEAC Network of Excellence. Jaume Abella has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717.Peer ReviewedPostprint (author's final draft

Discovering Adaptable Symbolic Algorithms from Scratch

Autonomous robots deployed in the real world will need control policies that rapidly adapt to environmental changes. To this end, we propose AutoRobotics-Zero (ARZ), a method based on AutoML-Zero that discovers zero-shot adaptable policies from scratch. In contrast to neural network adaption policies, where only model parameters are optimized, ARZ can build control algorithms with the full expressive power of a linear register machine. We evolve modular policies that tune their model parameters and alter their inference algorithm on-the-fly to adapt to sudden environmental changes. We demonstrate our method on a realistic simulated quadruped robot, for which we evolve safe control policies that avoid falling when individual limbs suddenly break. This is a challenging task in which two popular neural network baselines fail. Finally, we conduct a detailed analysis of our method on a novel and challenging non-stationary control task dubbed Cataclysmic Cartpole. Results confirm our findings that ARZ is significantly more robust to sudden environmental changes and can build simple, interpretable control policies.Comment: Published as a conference paper at International Conference on Intelligent Robots and Systems (IROS) 2023. See https://youtu.be/sEFP1Hay4nE for associated video fil

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

Hardware in the loop, all-electronic wind turbine emulator for grid compliance testing

During the last years the distribution of renewable energy sources is continuously increasing and their influence on the distribution grid is becoming every year more relevant. As the increasing integration of renewable resources is radically changing the grid scenario, grid code technical requirements as are needed to ensure the grid correct behavior. To be standard compliant wind turbines need to be submitted to certification tests which usually must be performed on the field. One of the most difficult tests to be performed on the field is the low voltage ride through (LVRT) certitication due to the following resons: • The standards specify it must be performed ad different power levels. For this reasons it is necessary to wait for the right atmospheric conditions. • It requires a voltage sag generator which is usually expensive and bulky. • The voltage sag generator needs to be cabled between the grid and the wind turbine. • The voltage sag generator causes disturbances and perturbation on the power grid, for this reasons agreements with the distributor operator are needed. For all these reasons a laboratory test bench to perform the LVRT certification tests on wind turbines would be a more controlled and inexpensive alternative to the classic testing methodology. The research presented in this thesis is focused on the design and the realization of a test bench to perform certification tests on energy converters for wind turbines in laboratory. More specifically, the possibility of performing LVRT certification tests directly in laboratory over controlled conditions would allow faster testing procedures and less certification overall costs. The solution presented in this thesis is based on a power hardware in the loop implementing a digitally-controlled, power electronics-based emulation of a wind turbine. This emulator is used to drive the electronic wind energy converter (WEC) under test. A grid emulator is used to apply voltage sags to the wind turbine converter and perform LVRT certification tests. In this solution AC power supplies are used to emulate both the wind turbine and the grid emulator. For this reason the test bench power rating is limited to the AC supplies one. Two working versions of the test bench has been realized and successfully tested. The work here presented has evolved through the following phases: • Study of the grid code requirements and the state of the art. • Modeling of the parts of a wind turbine and complete system simulations