60 research outputs found
Toatie : functional hardware description with dependent types
Describing correct circuits remains a tall order, despite four decades of evolution in Hardware Description Languages (HDLs).
Many enticing circuit architectures require recursive structures or complex compile-time computation — two patterns that prove difficult to capture in traditional HDLs. In a signal processing context, the Fast FIR Algorithm (FFA) structure for efficient parallel filtering proves to be naturally recursive, and most Multiple Constant Multiplication (MCM) blocks decompose multiplications into graphs of simple shifts and adds using demanding compile time computation. Generalised versions of both remain mostly in academic folklore. The implementations which do exist are often ad hoc circuit generators, written in software languages. These pose challenges for verification and are resistant to composition.
Embedded functional HDLs, that represent circuits as data, allow for these descriptions at the cost of forcing the designer to work at the gate-level. A promising alternative is to use a stand-alone compiler, representing circuits as plain functions, exemplified by the CλaSH HDL. This, however, raises new challenges in capturing a circuit’s staging — which expressions in the single language should be reduced during compile-time elaboration, and which should remain in the circuit’s run-time? To better reflect the physical separation between circuit phases, this work proposes a new functional HDL (representing circuits as functions) with first-class staging constructs.
Orthogonal to this, there are also long-standing challenges in the verification of parameterised circuit families. Industry surveys have consistently reported that only a slim minority of FPGA projects reach production without non-trivial bugs. While a healthy growth in the adoption of automatic formal methods is also reported, the majority of testing remains dynamic — presenting difficulties for testing entire circuit families at once.
This research offers an alternative verification methodology via the combination of dependent types and automatic synthesis of user-defined data types. Given precise enough types for synthesisable data, this environment can be used to develop circuit families with full functional verification in a correct-by-construction fashion. This approach allows for verification of entire circuit families (not just one concrete member) and side-steps the state-space explosion of model checking methods. Beyond the existing work, this research offers synthesis of combinatorial circuits — not just a software model of their behaviour. This additional step requires careful consideration of staging, erasure & irrelevance, deriving bit representations of user-defined data types, and a new synthesis scheme.
This thesis contributes steps towards HDLs with sufficient expressivity for awkward, combinatorial signal processing structures, allowing for a correct-by-construction approach, and a prototype compiler for netlist synthesis.Describing correct circuits remains a tall order, despite four decades of evolution in Hardware Description Languages (HDLs).
Many enticing circuit architectures require recursive structures or complex compile-time computation — two patterns that prove difficult to capture in traditional HDLs. In a signal processing context, the Fast FIR Algorithm (FFA) structure for efficient parallel filtering proves to be naturally recursive, and most Multiple Constant Multiplication (MCM) blocks decompose multiplications into graphs of simple shifts and adds using demanding compile time computation. Generalised versions of both remain mostly in academic folklore. The implementations which do exist are often ad hoc circuit generators, written in software languages. These pose challenges for verification and are resistant to composition.
Embedded functional HDLs, that represent circuits as data, allow for these descriptions at the cost of forcing the designer to work at the gate-level. A promising alternative is to use a stand-alone compiler, representing circuits as plain functions, exemplified by the CλaSH HDL. This, however, raises new challenges in capturing a circuit’s staging — which expressions in the single language should be reduced during compile-time elaboration, and which should remain in the circuit’s run-time? To better reflect the physical separation between circuit phases, this work proposes a new functional HDL (representing circuits as functions) with first-class staging constructs.
Orthogonal to this, there are also long-standing challenges in the verification of parameterised circuit families. Industry surveys have consistently reported that only a slim minority of FPGA projects reach production without non-trivial bugs. While a healthy growth in the adoption of automatic formal methods is also reported, the majority of testing remains dynamic — presenting difficulties for testing entire circuit families at once.
This research offers an alternative verification methodology via the combination of dependent types and automatic synthesis of user-defined data types. Given precise enough types for synthesisable data, this environment can be used to develop circuit families with full functional verification in a correct-by-construction fashion. This approach allows for verification of entire circuit families (not just one concrete member) and side-steps the state-space explosion of model checking methods. Beyond the existing work, this research offers synthesis of combinatorial circuits — not just a software model of their behaviour. This additional step requires careful consideration of staging, erasure & irrelevance, deriving bit representations of user-defined data types, and a new synthesis scheme.
This thesis contributes steps towards HDLs with sufficient expressivity for awkward, combinatorial signal processing structures, allowing for a correct-by-construction approach, and a prototype compiler for netlist synthesis
Algorithm to layout (ATL) systems for VLSI design
PhD ThesisThe complexities involved in custom VLSI design together with the
failure of CAD techniques to keep pace with advances in the fabrication
technology have resulted in a design bottleneck. Powerful tools are
required to exploit the processing potential offered by the densities now
available. Describing a system in a high level algorithmic notation
makes writing, understanding, modification, and verification of a design
description easier. It also removes some of the emphasis on the physical
issues of VLSI design, and focus attention on formulating a correct and
well structured design. This thesis examines how current trends in CAD
techniques might influence the evolution of advanced Algorithm To Layout
(ATL) systems. The envisaged features of an example system are
specified. Particular attention is given to the implementation of one
its features COPTS (Compilation Of Occam Programs To Schematics).
COPTS is capable of generating schematic diagrams from which an
actual layout can be derived. It takes a description written in a subset
of Occam and generates a high level schematic diagram depicting its
realisation as a VLSI system. This diagram provides the designer with
feedback on the relative placement and interconnection of the operators
used in the source code. It also gives a visual representation of the
parallelism defined in the Occam description. Such diagrams are a
valuable aid in documenting the implementation of a design.
Occam has also been selected as the input to the design system that
COPTS is a feature of. The choice of Occam was made on the assumption
that the most appropriate algorithmic notation for such a design system
will be a suitable high level programming language. This is in contrast
to current automated VLSI design systems, which typically use a hardware
des~ription language for input. These special purpose languages
currently concentrate on handling structural/behavioural information and
have limited ability to express algorithms. Using a language such as
Occam allows a designer to write a behavioural description which can be
compiled and executed as a simulator, or prototype, of the system. The
programmability introduced into the design process enables designers to
concentrate on a design's underlying algorithm. The choice of this
algorithm is the most crucial decision since it determines the
performance and area of the silicon implementation.
The thesis is divided into four sections, each of several chapters.
The first section considers VLSI design complexity, compares the expert
systems and silicon compilation approaches to tackling it, and examines
its parallels with software complexity. The second section reviews the
advantages of using a conventional programming language for VLSI system
descriptions. A number of alternative high level programming languages
are considered for application in VLSI design. The third section defines
the overall ATL system COPTS is envisaged to be part of, and considers
the schematic representation of Occam programs. The final section
presents a summary of the overall project and suggestions for future work
on realising the full ATL system
A Formal, Hierarchical Design and Validation Methodology for VLSI
The high cost of fabricating VLSI circuits requires that they be validated, that is,
shown to function correctly, before manufacture. The cost of design errors can be
kept to a minimum if such validation occurs as early as possible; this is achieved
by integrating validation into a hierarchical design procedure.
In this thesis, a hierarchical approach to design, in which validation is performed
between each pair of adjacent levels in the hierarchy, is developed. In
order to adopt such an approach, a language is required for the formal description
of hardware behaviour and structure. Therefore an important aspect of the development
of the methodology, and a major theme of the thesis, is the development
of languages to support the methodology. An enhanced version of CIRCAL, which
enables large and abstract devices to be described concisely and supports formal
reasoning about the behaviour of constructed systems, is presented.
Specifications should accurately model the behaviour of real hardware and
should be useful for design and validation; they should also be easy to write.
In order to realise these goals, a number of specification techniques have been
developed and a new language which enforces some of these techniques, thereby
easing the specification task, is proposed.
Ways in which a language may assist design have been investigated. Language
constructs which restrict a designer, thereby removing some design decisions, have
been developed. A simple correctness-preserving transformation is presented, illustrating
another way in which a designer may be assisted by a formal language.
Specification techniques play an important part in the validation task, as accurate
and consistent modelling is vital in establishing the correctness of implementations.
Techniques have also been developed which enable detailed implementations
to be usefully compared with more abstract specifications. This is demonstrated
in a large example, the specification, design and formal verification of a simple
microprocessor.
Finally, the concept of contextual constraints, restrictions on the environment
in which a device may be placed, is introduced. A method of specifying such
constraints has been developed, and it is shown that their formal treatment can
provide assistance in specification, design and verification
Static Analysis of Circuits for Security
The purpose of the present work is to define a methodology to analyze a system description given in VHDL code and test its security properties. In particular the analysis is aimed at ensuring that a malicious user cannot make a circuit output the secret data it contains
Generation of Application Specific Hardware Extensions for Hybrid Architectures: The Development of PIRANHA - A GCC Plugin for High-Level-Synthesis
Architectures combining a field programmable gate array (FPGA) and a general-purpose processor on a single chip became increasingly popular in recent years. On the one hand, such hybrid architectures facilitate the use of application specific hardware accelerators that improve the performance of the software on the host processor. On the other hand, it obliges system designers to handle the whole process of hardware/software co-design. The complexity of this process is still one of the main reasons, that hinders the widespread use of hybrid architectures. Thus, an automated process that aids programmers with the hardware/software partitioning and the generation of application specific accelerators is an important issue. The method presented in this thesis neither requires restrictions of the used high-level-language nor special source code annotations. Usually, this is an entry barrier for programmers without deeper understanding of the underlying hardware platform.
This thesis introduces a seamless programming flow that allows generating hardware accelerators for unrestricted, legacy C code. The implementation consists of a GCC plugin that automatically identifies application hot-spots and generates hardware accelerators accordingly. Apart from the accelerator implementation in a hardware description language, the compiler plugin provides the generation of a host processor interfaces and, if necessary, a prototypical integration with the host operating system. An evaluation with typical embedded applications shows general benefits of the approach, but also reveals limiting factors that hamper possible performance improvements
Asynchrobatic logic for low-power VLSI design
In this work, Asynchrobatic Logic is presented. It is a novel low-power
design style that combines the energy saving benefits of asynchronous logic
and adiabatic logic to produce systems whose power dissipation is reduced in
several different ways. The term “Asynchrobatic” is a new word that can be
used to describe these types of systems, and is derived from the
concatenation and shortening of Asynchronous, Adiabatic Logic. This thesis
introduces the concept and theory behind Asynchrobatic Logic. It first
provides an introductory background to both underlying parent technologies
(asynchronous logic and adiabatic logic). The background material continues
with an explanation of a number of possible methods for designing complex
data-path cells used in the adiabatic data-path. Asynchrobatic Logic is then
introduced as a comparison between asynchronous and Asynchrobatic buffer
chains, showing that for wide systems, it operates more efficiently. Two
more-complex sub-systems are presented, firstly a layout implementation of
the substitution boxes from the Twofish encryption algorithm, and secondly a
front-end only (without parasitic capacitances, resistances) simulation that
demonstrates a functional system capable of calculating the Greatest
Common Denominator (GCD) of a pair of 16-bit unsigned integers, which
under typical conditions on a 0.35μm process, executed a test vector requiring
twenty-four iterations in 2.067μs with a power consumption of 3.257nW.
These examples show that the concept of Asynchrobatic Logic has the
potential to be used in real-world applications, and is not just theory without
application. At the time of its first publication in 2004, Asynchrobatic Logic
was both unique and ground-breaking, as this was the first time that
consideration had been given to operating large-scale adiabatic logic in an
asynchronous fashion, and the first time that Asynchronous Stepwise
Charging (ASWC) had been used to drive an adiabatic data-path
On microelectronic self-learning cognitive chip systems
After a brief review of machine learning techniques and applications, this Ph.D. thesis examines several approaches for implementing machine learning architectures and algorithms into hardware within our laboratory.
From this interdisciplinary background support, we have motivations for novel approaches that we intend to follow as an objective of innovative hardware implementations of dynamically self-reconfigurable logic for enhanced self-adaptive, self-(re)organizing and eventually self-assembling machine learning systems, while developing this new particular area of research.
And after reviewing some relevant background of robotic control methods followed by most recent advanced cognitive controllers, this Ph.D. thesis suggests that amongst many well-known ways of designing operational technologies, the design methodologies of those leading-edge high-tech devices such as cognitive chips that may well lead to intelligent machines exhibiting
conscious phenomena should crucially be restricted to extremely well defined constraints.
Roboticists also need those as specifications to help decide upfront on otherwise infinitely free hardware/software design details.
In addition and most importantly, we propose these specifications as methodological guidelines tightly related to ethics and the nowadays well-identified workings of the human body and of its psyche
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