Investigation on Performance Metrics of Nanoscale Multigate MOSFETs towards RF and IC Applications

Silicon-on-Insulator (SOI) MOSFETs have been the primary precursor for the CMOS technology since last few decades offering superior device performance in terms of package density, speed, and reduced second order harmonics. Recent trends of investigation have stimulated the interest in Fully Depleted (FD) SOI MOSFET because of their remarkable scalability efficiency. However, some serious issues like short channel effects (SCEs) viz drain induced barrier lowering (DIBL), Vth roll-off, subthreshold slope (SS), and hot carrier effects (HCEs) are observed in nanoscale regime. Numerous advanced structures with various engineering concepts have been addressed to reduce the above mentioned SCEs in SOI platform. Among them strain engineering, high-k gate dielectric with metal gate technology (HKMG), and non-classical multigate technologies are most popular models for enhancement in carrier mobility, suppression of gate leakage current, and better immunization to SCEs. In this thesis, the performance of various emerging device designs are analyzed in nanoscale with 2-D modeling as well as through calibrated TCAD simulation. These attempts are made to reduce certain limitations of nanoscale design and to provide a significant contribution in terms of improved performances of the miniaturized devices. Various MOS parameters like gate work function (_m), channel length (L), channel thickness (tSi), and gate oxide thickness (tox) are optimized for both FD-SOI and Multiple gate technology. As the semiconductor industries migrate towards multigate technology for system-on-chip (SoC), system-in-package (SiP), and internet-of-things (IoT) applications, an appropriate examination of the advanced multiple gate MOFETs is required for the analog/RF application keeping reliability issue in mind. Various non-classical device structures like gate stack engineering and halo doping in the channel are extensively studied for analog/RF applications in double gate (DG) platform. A unique attempt has been made for detailed analysis of the state-of-the-art 3-D FinFET on dependency of process variability. The 3-D architecture is branched as Planar or Trigate or FinFET according to the aspect ratio (WFin=HFin). The evaluation of zero temperature coefficient (ZTC) or temperature inflection point (TCP) is one of the key investigation of the thesis for optimal device operation and reliability. The sensitivity of DG-MOSFET and FinFET performances have been addressed towards a wide range of temperature variations, and the ZTC points are identified for both the architectures. From the presented outcomes of this work, some ideas have also been left for the researchers for design of optimum and reliable device architectures to meet the requirements of high performance (HP) and/or low standby power (LSTP) applications

Design Strategies for Ultralow Power 10nm FinFETs

Integrated circuits and microprocessor chips have become integral part of our everyday life to such an extent that it is difficult to imagine a system related to consumer electronics, health care, public transportation, household application without these small components. The heart of these circuits is, the metal oxide field-effect transistor (MOSFET) which is used as a switch. The dimensions of these transistors have been scaled from a few micrometers to few tens of nanometer to achieve higher performance, lower power consumption and low cost of production. According to the International Technology Roadmap for Semiconductors (ITRS), beyond 32 nm technology node, planer devices will not be able to fulfill the strict leakage requirement anymore due to overpowering short channel effects and need of multi-gate transistor is inevitable. The motivation of the thesis therefore is to investigate techniques to engineer threshold voltage of a tri-gate FinFET for low power and ultra-low power applications. The complexity of physics involved in 3D nano- devices encourages use of advanced simulation tools. Thus, Technology Computer Aided Design Tools (TCAD) are needed to perform device optimization and support device and process integration engineers. Below 20nm technology node, the Fin-shaped Field Effect Transistor or Tri-gate transistor requires extensive use of 3D TCAD simulations. The multi-gate devices such as FinFETs are considered to be one of the most promising devices for Ultra Large Scale Integration (ULSI). This device structural design with additional gate electrodes and channel surfaces offers dynamic threshold voltage control. In addition, it can provide better short channel performance and reduced leakage. In this study, new design strategies for 10nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (50pA/μ

Multilevel 3-D Device Simulation Approach Applied to Deeply Scaled Nanowire Field Effect Transistors

Three silicon nanowire (SiNW) field effect transistors (FETs) with 15 -, 12.5 -and 10.6 -nm gate lengths are simulated using hierarchical multilevel quantum and semiclassical models verified against experimental ID – VG characteristics. The tight-binding (TB) formalism is employed to obtain the band structure in k -space of ellipsoidal NWs to extract electron effective masses. The masses are transferred into quantum-corrected 3-D finite element (FE) drift-diffusion (DD) and ensemble Monte Carlo (MC) simulations, which accurately capture the quantum-mechanical confinement of the ellipsoidal NW cross sections. We demonstrate that the accurate parameterization of the bandstructure and the quantum-mechanical confinement has a profound impact on the computed ID – VG characteristics of nanoscaled devices. Finally, we devise a step-by-step technology computer-aided design (TCAD) methodology of simple parameterization for efficient DD device simulations

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

Multigate MOSFETs for digital performance and high linearity, and their fabrication techniques

The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology is facing great challenges to overcome severe short-channel effects. Multigate MOSFETs are one of the most promising candidates for scaling beyond Si CMOS, due to better electrostatic control as compared to conventional planar MOSFETs. Conventional dry etching-induced surface damage is one of the main sources of performance degradation for multigate transistors, especially for III-V high mobility materials. It is also challenging to increase the fin aspect ratio by dry etching because of the non-ideal anisotropic etching profile. Here, we report a novel method, inverse metal-assisted chemical etching (i-MacEtch), in lieu of conventional RIE etching, for 3D fin channel formation. InP junctionless FinFETs with record high-aspect-ratio (~ 50:1) fins are demonstrated by this method for the first time. The i-MacEtch process flow eliminates dry-etching-induced plasma damage, high energy ion implantation damage, and high temperature annealing, allowing for the fabrication of InP fin channels with atomically smooth sidewalls. The sidewall features resulting from this unique and simplified process ensure high interface quality between high-k dielectric layer and InP fin channel. Experimental and theoretical analyses show that high-aspect-ratio FinFETs, which could deliver more current per area under much relaxed horizontal geometry requirements, are promising in pushing the technology node ahead where conventional scaling has met its physical limits. The performance of the FinFET was further investigated through numerical simulation. A new kind of FinFET with asymmetric gate and source/drain contacts has been proposed and simulated. By benchmarking with conventional symmetric FinFET, better short-channel behavior with much higher current density is confirmed. The design guidelines are provided. The overall circuit delay can be minimized by optimizing gate lengths according to different local parasites among circuits in interconnection-delay-dominated SoC applications. Continued transistor scaling requires even stronger gate electrostatic control over the channel. The ultimate scaling structure would be gate-all-around nanowire MOSFETs. We demonstrate III-V junctionless gate-all-around (GAA) nanowire (NW) MOSFETs for the first time. For the first time, source/drain (S/D) resistance and thermal budget are minimized by regrowth using metalorganic chemical vapor deposition (MOCVD) in III-V MOSFETs. The fabricated short-channel (Lg=80 nm) GaAs GAA NWFETs with extremely narrow nanowire width (WNW= 9 nm) show excellent transconductance (gm) linearity at biases (300 mV), characterized by the high third intercept point (2.6 dBm). The high linearity is especially important for low power applications because it is insensitive to bias conditions

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach

Variability analysis of FinFET AC/RF performances through efficient physics-based simulations for the optimization of RF CMOS stages

A nearly insatiable appetite for the latest electronic device enables the electronic technology sector to maintain research momentum. The necessity for advancement with miniaturization of electronic devices is the need of the day. Aggressive downscaling of electronic devices face some fundamental limits and thus, buoy up the change in device geometry. MOSFETs have been the leading contender in the electronics industry for years, but the dire need for miniaturization is forcing MOSFET to be scaled to nano-scale and in sub-50 nm scale. Short channel effects (SCE) become dominant and adversely affect the performance of the MOSFET. So, the need for a novel structure was felt to suppress SCE to an acceptable level. Among the proposed devices, FinFETs (Fin Field Effect Transistors) were found to be most effective to counter-act SCE in electronic devices. Today, many industries are working on electronic circuits with FinFETs as their primary element.One of limitation which FinFET faces is device variability. The purpose of this work was to study the effect that different sources of parameter fluctuations have on the behavior and characteristics of FinFETs. With deep literature review, we have gained insight into key sources of variability. Different sources of variations, like random dopant fluctuation, line edge roughness, fin variations, workfunction variations, oxide thickness variation, and source/drain doping variations, were studied and their impact on the performance of the device was studied as well. The adverse effect of these variations fosters the great amount of research towards variability modeling. A proper modeling of these variations is required to address the device performance metric before the fabrication of any new generation of the device on the commercial scale. The conventional methods to address the characteristics of a device under variability are Monte-Carlo-like techniques. In Monte Carlo analysis, all process parameters can be varied individually or simultaneously in a more realistic approach. The Monte Carlo algorithm takes a random value within the range of each process parameter and performs circuit simulations repeatedly. The statistical characteristics are estimated from the responses. This technique is accurate but requires high computational resources and time. Thus, efforts are being put by different research groups to find alternative tools. If the variations are small, Green’s Function (GF) approach can be seen as a breakthrough methodology. One of the most open research fields regards "Variability of FinFET AC performances". One reason for the limited AC variability investigations is the lack of commercially available efficient simulation tools, especially those based on accurate physics-based analysis: in fact, the only way to perform AC variability analysis through commercial TCAD tools like Synopsys Sentaurus is through the so-called Monte Carlo approach, that when variations are deterministic, is more properly referred to as incremental analysis, i.e., repeated solutions of the device model with varying physical parameters. For each selected parameter, the model must be solved first in DC operating condition (working point, WP) and then linearized around the WP, hence increasing severely the simulation time. In this work, instead, we used GF approach, using our in-house Simulator "POLITO", to perform AC variability analysis, provided that variations are small, alleviating the requirement of double linearization and reducing the simulation time significantly with a slight trade-off in accuracy. Using this tool we have, for the first time addressed the dependency of FinFET AC parameters on the most relevant process variations, opening the way to its application to RF circuits. This work is ultimately dedicated to the successful implementation of RF stages in commercial applications by incorporating variability effects and controlling the degradation of AC parameters due to variability. We exploited the POLITO (in-house simulator) limited to 2D structures, but this work can be extended to the variability analysis of 3D FinFET structure. Also variability analysis of III-V Group structures can be addressed. There is also potentiality to carry out the sensitivity analysis for the other source of variations, e.g., thermal variations

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (L G ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to L G of 16 nm offering a larger on-current (I ON ) and slightly better sub-threshold characteristics. Below L G of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current (I OFF ), and the largest I ON /I OFF ratio out of the three architectures. However, the NW FET suffers from early ION saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device bodyThis work was supported in part by the Spanish Government under Project TIN2013-41129-P and Project TIN2016-76373-P, in part by the Xunta de Galicia and FEDER Funds under Grant GRC 2014/008, and in part by the Consellería de Cultura, Educación e Ordenación Universitaria (accreditation 2016–2019) under Grant ED431G/08. The work of Guillermo Indalecio was supported by the Programa de Axudas á Etapa Posdoutoral da Xunta de Galicia under Grant 2017/077. The work of Natalia Seoane was supported by the RyC Programme of the Spanish Ministerio de Ciencia, Innovación y Universidades under Grant RYC-2017-23312S

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length ( LG ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to LG of 16 nm offering a larger on-current ( ION ) and slightly better sub-threshold characteristics. Below LG of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current ( IOFF ), and the largest ION/IOFF ratio out of the three architectures. However, the NW FET suffers from early ION saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body