Digital Twins: Review and Challenges

[EN] With the arises of Industry 4.0, numerous concepts have emerged; one of the main concepts is the digital twin (DT). DT is being widely used nowadays, however, as there are several uses in the existing literature; the understanding of the concept and its functioning can be diffuse. The main goal of this paper is to provide a review of the existing literature to clarify the concept, operation, and main characteristics of DT, to introduce the most current operating, communication, and usage trends related to this technology, and to present the performance of the synergy between DT and multi-agent system (MAS) technologies through a computer science approach.This work was partly supported by the Spanish Government (RTI2018-095390-B-C31)Juárez-Juárez, MG.; Botti, V.; Giret Boggino, AS. (2021). Digital Twins: Review and Challenges. Journal of Computing and Information Science in Engineering. 21(3):1-23. https://doi.org/10.1115/1.405024412321

2012-13 Graduate Bulletin

After 2003 the University of Dayton Bulletin went exclusively online. This copy was downloaded from the University of Dayton\u27s website.https://ecommons.udayton.edu/bulletin_grad/1007/thumbnail.jp

2001-2002 Bulletin

Volume 112, Number 4 Scanned from the copy held in University Archives and Special Collections.https://ecommons.udayton.edu/bulletin/1069/thumbnail.jp

2000-2001 Bulletin

Volume 111, Number 4. Scanned from the copy held in the Registrar\u27s Office.https://ecommons.udayton.edu/bulletin/1046/thumbnail.jp

1999-2000 Bulletin

Volume 110, Number 4 Scanned from the copy held in University Archives and Special Collections.https://ecommons.udayton.edu/bulletin/1068/thumbnail.jp

1998-1999 Bulletin

Volume 109, Number 4 Scanned from the copy held in University Archives and Special Collections.https://ecommons.udayton.edu/bulletin/1067/thumbnail.jp

2013-14 Graduate Bulletin

After 2003 the University of Dayton Bulletin went exclusively online. This copy was downloaded from the University of Dayton\u27s website.https://ecommons.udayton.edu/bulletin_grad/1008/thumbnail.jp

1996-1997 Bulletin

Volume 106, Number 1 Scanned from the copy held in the Registrar\u27s Office. The Electrical and Computer Engineering inserts are located in the beginning of the bulletin.https://ecommons.udayton.edu/bulletin_grad/1028/thumbnail.jp

1993-1994 Bulletin

Volume 104, Number 4 Scanned from the copy held in University Archives and Special Collections.https://ecommons.udayton.edu/bulletin/1065/thumbnail.jp

Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip

The sustained demand for faster, more powerful chips has been met by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the onchip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation performs a design space exploration of network-on-chip architectures, in order to point-out the trade-offs associated with the design of each individual network building blocks and with the design of network topology overall. The design space exploration is preceded by a comparative analysis of state-of-the-art interconnect fabrics with themselves and with early networkon- chip prototypes. The ultimate objective is to point out the key advantages that NoC realizations provide with respect to state-of-the-art communication infrastructures and to point out the challenges that lie ahead in order to make this new interconnect technology come true. Among these latter, technologyrelated challenges are emerging that call for dedicated design techniques at all levels of the design hierarchy. In particular, leakage power dissipation, containment of process variations and of their effects. The achievement of the above objectives was enabled by means of a NoC simulation environment for cycleaccurate modelling and simulation and by means of a back-end facility for the study of NoC physical implementation effects. Overall, all the results provided by this work have been validated on actual silicon layout