Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Characterisation and noise analysis of high Ge content p-channel SiGe MOSFETs fabricated using virtual substrates

This thesis demonstrates the advantages and disadvantages of investigated p-type SiGe MOSFETs with high Ge content Si1#xGex p-channel grown on Si1#yGey virtual substrate (VS) (x "0'7$0'9, y "0'3$0'5) in comparison with conventional Si devices. The ways to overcome current difficulties in conventional Si technology and mixed SiGe-Si technology are shown. Current-voltage (I-V) and capacitance-voltage (C-V) DC characteristics for p-channel Si/Si1#xGex/Si1#yGey hetero-MOSFETs with high Ge content (x "0'7$0'9, y"0'3$0'5) are reported. Enhancement in the maximum drain current for the p-SiGe devices in comparison with p-Si control is 2.5-3.0 times. DC characteristic simulations of SiGe p-channel MOSFETs were used to improve the accuracy of MOSFET and heterostructure parameters extraction. Calibrated during the simulation theoretical models were used for future design. The effective mobility, the source-drain access resistance, the doping profile, the layers thickness, oxide/semiconductor interface charge and other important characteristics were extracted. The effective mobility values, extracted for p-Si0%3Ge0%7 MOSFETs, exceed the hole mobility in a conventional Si p-MOS device by a factor of 3.5 and reach the mobility of conventional Si n-MOS transistors. The peak value of me f f = 760 cm2V#1s#1 at field 0.08 MVcm#1 was obtained for p-Si/Si0%2Ge0%8/ Si0%5Ge0%5 MOSFETs. Efficiency of special n-type doped layer, also known as "punch-through" stopper, introduced into heterostructure is shown. Perfect I-V and also low frequency noise characteristics of investigated MOSFET show that the p-type Si/Si1#xGex/Si1#yGey (x "0'7 $0'9, x$y "0'3$0'4) heterostructures with "punch-through" stopper could be very impressive opportunity to conventional Si for modern semiconductor industry. For the first time, quantitative explanation of the low frequency noise reduction in metamorphic, high Ge content, SiGe p-MOSFETs compared to Si p-MOSFETs have been proposed. Quantitative analysis demonstrates the importance of both carrier number fluctuations and correlated mobility fluctuations (CMF) components to the 1/ f noise of surface channel Si p-MOSFET, but the absence of CMF for buried channel p-Si0%3Ge0%7 and p- Si0%2Ge0%8 MOSFETs. The low frequency noise was measured to be three times smaller for a 0.55 mm effective gate length p-Si0%3Ge0%7 MOSFET than the Si control, at linear regime (VDS = -50 mV) and high gate overdrive voltage (Vgt= -1.5 V). This result is very important, because we have reduction in LF noise at high gate overdrive voltages, which are typical for analogue and power electronics application. Both DC and low frequency noise characteristics show that access source and drain resistance for metamorphic p-SiGe MOSFETs (RS +RD ,1.5-2.0kW !mm) roughly 2 times lower then for conventional p-Si MOSFETs

Hot carrier degradation in deep submicron n-MOS technologies

With the aggressive scaling of MOS devices hot carrier degradation continues to be a major reliability concern. The LDD technologies, which have been used to minimise the hot carrier damage in MOS devices, suffer from the spacer damage causing the drain series resistance degradation, along with the channel mobility degradation. Therefore, in order to optimise the performance and reliability of these technologies it is necessary to quantify the roles of spacer and channel damages in determining their degradation behaviour. In this thesis the hot carrier degradation behaviour of different generations of graded drain (lightly doped, mildly doped and highly doped) n-MOS technologies, designed for 5V, 3V and 2V operation is investigated. The stress time beginning from microseconds is investigated to study how the damage initiates and evolves over time. A technology dependent two-stage degradation behaviour in the measured transconductance with an early stage deviating from conventionally observed power law behaviour is reported. A methodology based on conventional extraction procedure using the L-array method is first developed to analyse the drain series resistance and the mobility degradation. For 5V technologies the analysis of the damage using this methodology shows a two-stage drain series resistance degradation with early stage lasting about lOOms. However, it is seen that the conventional series resistance and mobility degradation methodology fails to satisfactorily predict degradation behaviour of 3V and 2V technologies, resulting in unphysical decreasing extracted series resistance. It is shown that after the hot carrier stress a change in the universal mobility behaviour for channel lengths approaching quarter micron regime has a significant effect on the parameter extraction. A modified universal mobility model incorporating the effect of the interface charge is developed using the FN stress experiments. A new generalised extraction methodology modelling hot carrier stressed device as series combination of undamaged and damaged channel regions, along with the series source drain resistance is developed, incorporating the modified universal model in the damaged channel region. The new methodology has the advantage of being single device based and serves as an effective tool in evaluating. the roles of series resistance and mobility degradations for technology qualification. This is especially true for the deep submicron regime where the conventional extraction procedures are not applicable. Further, the new extraction method has the potential of being integrated into commercial device simulation tools, to accurately analyse the device degradation behaviour in deep submicron regime