Resilience Strategies for Network Challenge Detection, Identification and Remediation

The enormous growth of the Internet and its use in everyday life make it an attractive target for malicious users. As the network becomes more complex and sophisticated it becomes more vulnerable to attack. There is a pressing need for the future internet to be resilient, manageable and secure. Our research is on distributed challenge detection and is part of the EU Resumenet Project (Resilience and Survivability for Future Networking: Framework, Mechanisms and Experimental Evaluation). It aims to make networks more resilient to a wide range of challenges including malicious attacks, misconfiguration, faults, and operational overloads. Resilience means the ability of the network to provide an acceptable level of service in the face of significant challenges; it is a superset of commonly used definitions for survivability, dependability, and fault tolerance. Our proposed resilience strategy could detect a challenge situation by identifying an occurrence and impact in real time, then initiating appropriate remedial action. Action is autonomously taken to continue operations as much as possible and to mitigate the damage, and allowing an acceptable level of service to be maintained. The contribution of our work is the ability to mitigate a challenge as early as possible and rapidly detect its root cause. Also our proposed multi-stage policy based challenge detection system identifies both the existing and unforeseen challenges. This has been studied and demonstrated with an unknown worm attack. Our multi stage approach reduces the computation complexity compared to the traditional single stage, where one particular managed object is responsible for all the functions. The approach we propose in this thesis has the flexibility, scalability, adaptability, reproducibility and extensibility needed to assist in the identification and remediation of many future network challenges

Characterization of an Integrated Circuit with Respect to Electrostatic Discharge-Induced Soft Failures

This research proposal presents a methodology whereby an integrated circuit (IC) can be characterized with respect to soft-failures induced by Electrostatic Discharge (ESD)-like events. This methodology uses an exclusively black-box approach to determine the response of an IC in a system-level environment, thereby allowing it to be implemented without intimate knowledge of the DUT IC. Results from this methodology can be referenced during system design to raise awareness of specific vulnerabilities of the core system ICs. During work on this methodology, several sub topics have been explored and developed in the field of system-level ESD. Sections 2 and 3 introduce two topics which were developed to facilitate the generation and expression of IC pin models. Papers 1 and 2 introduce injection methods for characterizing complete systems on an interface-by-interface basis and form the foundation for the following works. Papers 2 and 3 mirror Papers 1 and 2 but instead shift focus away from the system as a whole and outline methods for characterizing the integrated circuits directly. Finally, Section 4 outlines a model method which can be used to describe the failures found in Paper 4 in circuit simulation, rounding out the work. Additional measurements which were unable to be included in Paper 4 are included in Appendices A, B, and C --Abstract, page iv