Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated

Design of the Annular Suspension and Pointing System (ASPS) (including design addendum)

The Annular Suspension and Pointing System is an experiment pointing mount designed for extremely precise 3 axis orientation of shuttle experiments. It utilizes actively controlled magnetic bearing to provide noncontacting vernier pointing and translational isolation of the experiment. The design of the system is presented and analyzed

Full field image ranger hardware

We describe the hardware designed to implement a full field heterodyning imaging system. Comprising three key components - a light source, high speed shutter and a signal generator - the system is expected to be capable of simultaneous range measurements to millimetre precision over the entire field of view. Current modulated laser diodes provide the required illumination, with a bandwidth of 100 MHz and peak output power exceeding 600 mW. The high speed shutter action is performed by gating the cathode of an image intensifier, driven by a 50 Vpp waveform with 3.5 ns rise and fall times. A direct digital synthesiser, with multiple synchronised channels, provides high stability between its outputs, 160 MHz bandwidth and tuning of 0.1 Hz

A Novel Boost Converter Based LED Driver Chip Targeting Mobile Applications

abstract: A novel integrated constant current LED driver design on a single chip is developed in this dissertation. The entire design consists of two sections. The first section is a DC-DC switching regulator (boost regulator) as the frontend power supply; the second section is the constant current LED driver system. In the first section, a pulse width modulated (PWM) peak current mode boost regulator is utilized. The overall boost regulator system and its related sub-cells are explained. Among them, an original error amplifier design, a current sensing circuit and slope compensation circuit are presented. In the second section – the focus of this dissertation – a highly accurate constant current LED driver system design is unveiled. The detailed description of this highly accurate LED driver system and its related sub-cells are presented. A hybrid PWM and linear current modulation scheme to adjust the LED driver output currents is explained. The novel design ideas to improve the LED current accuracy and channel-to-channel output current mismatch are also explained in detail. These ideas include a novel LED driver system architecture utilizing 1) a dynamic current mirror structure and 2) a closed loop structure to keep the feedback loop of the LED driver active all the time during both PWM on-duty and PWM off-duty periods. Inside the LED driver structure, the driving amplifier with a novel slew rate enhancement circuit to dramatically accelerate its response time is also presented.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

An Ultra Low Power Digital to Analog Converter Optimized for Small Format LCD Applications

Liquid crystal displays (LCDs) for mobile applications present a unique design challenge. These small format displays can be found primarily in cell phones and PDAs which are devices that have particularly stringent power requirements. At the same time, the displays are increasing in resolution with every generation. This is creating demand for new LCD display technologies. The predominant amorphous thin film transistor technology is no longer feasible in the new high resolution small format screens due to the fact that the displays require too many connections to the driver and the aperture ratios do not allow high density displays. New technologies such as low temperature polysilicon (LTPS) displays continue to shrink in size and increase in resolution. LTPS technology enables the display manufacturer to create relatively high quality transistors on the glass. This allows for a display architecture which integrates the gate driver on the glass. Newer LTPS LCDs also enable a high level of multiplexing the sources lines on the glass which allows for a much simpler connection to the display driver chip. The electronic drivers for these display applications must adhere to strict power and area budgets. This work describes a low-power, area efficient, scalable, digital-to-analog conversion (DAC) integrated circuit architecture optimized for driving small format LCDs. The display driver is based on a twelve channel, 9-bit DAC driver. This architecture, suitable for % VGA resolution displays, exhibited a 2 MSPS conversion rate, less than 300 pW power dissipation per channel using a 5 V supply, and a die area of 0.042 mm per DAC. A new performance standard is set for DAC display drivers in joules per bit areal density

PIRATE: A Remotely-Operable Telescope Facility for Research and Education

We introduce PIRATE, a new remotely-operable telescope facility for use in research and education, constructed from 'off-the-shelf' hardware, operated by The Open University. We focus on the PIRATE Mark 1 operational phase where PIRATE was equipped with a widely- used 0.35m Schmidt-Cassegrain system (now replaced with a 0.425m corrected Dall Kirkham astrograph). Situated at the Observatori Astronomic de Mallorca, PIRATE is currently used to follow up potential transiting extrasolar planet candidates produced by the SuperWASP North experiment, as well as to hunt for novae in M31 and other nearby galaxies. It is operated by a mixture of commercially available software and proprietary software developed at the Open University. We discuss problems associated with performing precision time series photometry when using a German Equatorial Mount, investigating the overall performance of such 'off-the-shelf' solutions in both research and teaching applications. We conclude that PIRATE is a cost-effective research facility, and also provides exciting prospects for undergraduate astronomy. PIRATE has broken new ground in offering practical astronomy education to distance-learning students in their own homes.Comment: Accepted for publication in PASP. 14 pages, 11 figure

A 6.7-GHz Active Gate Driver for GaN FETs to Combat Overshoot, Ringing, and EMI

Active gate driving has been demonstrated to beneficially shape switching waveforms in Si-and SiC-based power converters. For faster GaN power devices with sub-10-ns switching transients, however, reported variable gate driving has so far been limited to altering a single drive parameter once per switching event, either during or outside of the transient. This paper demonstrates a gate driver with a timing resolution and range of output resistance levels that surpass those of existing gate drivers or arbitrary waveform generators. It is shown to permit active gate driving with a bandwidth that is high enough to shape a GaN switching during the transient. The programmable gate driver has integrated high-speed memory, control logic, and multiple parallel output stages. During switching transients, the gate driver can activate a near-arbitrary sequence of pull-up or pull-down output resistances between 0.12 and 64 A hybrid of clocked and asynchronous control logic with 150-ps delay elements achieves an effective resistance update rate of 6.7 GHz during switching events. This active gate driver is evaluated in a 1-MHz bridge-leg converter using EPC2015 GaN FETs. The results show that aggressive manipulation of the gate-drive resistance at sub-nanosecond resolutions can profile gate waveforms of the GaN FET, thereby beneficially shaping the switch-node voltage waveform in the power circuit. Examples of open-loop active gate driving are demonstrated that maintain the low switching loss of constant-strength gate driving, while reducing overshoot, oscillation, and EMI-generating high-frequency spectral content

Comparison of conventional DAQ systems and embedded DAQ systems

M. Tech. (Electrical & Electronic Engineering)In this research we compare conventional data acquisition system (DAS) with the embedded data acquisition systems. The performance specifications of 4 different types of DAQ cards are drawn up with special emphasis made on the following parameters: Slew rate, settling time, relative accuracy and system noise. These parameters are taken from 2 conventional DAS and then compared to those taken from 2 embedded data acquisition systems under the same electrical conditions. The embedded DAQ system’s hardware was built using the PIC Microcontroller interfaced to the Digital to Analog Convertors (DAC). MPLAB C18 is used to create a program which communicates with the embedded DAQ system, to transmit generated signals. National Instrument's LabView is used to create a program which communicates with the conventional DAQ system, to acquire external generated signals and retransmit the signals. In most cases the performance of conventional and embedded are close, but one of the embedded DAS seem to be unstable at high frequencies

MODELING AND TEST OF THE EFFICIENCY OF ELECTRONIC SPEED CONTROLLERS FOR BRUSHLESS DC MOTORS

Small electric uninhabited aerial vehicles (UAV) represent a rapidly expanding market requiring optimization in both efficiency and weight; efficiency is critical during cruise or loiter where the vehicle operates at part power for up to 99% of the mission time. Of the four components (battery, motor, propeller, and electronic speed controller (ESC)) of the electric propulsion system used in small UAVs, the ESC has no accepted performance model and almost no published performance data. To collect performance data, instrumentation was developed to measure electrical power in and out of the ESC using the two wattmeter method and current sense resistors; data was collected with a differential simultaneous data acquisition system. Performance of the ESC was measured under different load, commanded throttle, bus voltage, and switching frequency, and it was found that ESC efficiency decreases with increasing torque and decreasing bus voltage and does not vary much with speed and switching frequency. The final instrumentation was limited to low-voltage systems and error propagation calculations indicate a great deal of error at low power measurements; despite these limitations, an understanding of ESC performance appropriate for conceptual design of these systems was obtained. MODELING AND TEST OF THE EFFICIENCY OF ELECTRONIC SPEED CONTROLLERS FOR BRUSHLESS DC MOTOR