190 research outputs found

    NASA SpaceCube Next-Generation Artificial-Intelligence Computing for STP-H9-SCENIC on ISS

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    Recently, Artificial Intelligence (AI) and Machine Learning (ML) capabilities have seen an exponential increase in interest from academia and industry that can be a disruptive, transformative development for future missions. Specifically, AI/ML concepts for edge computing can be integrated into future missions for autonomous operation, constellation missions, and onboard data analysis. However, using commercial AI software frameworks onboard spacecraft is challenging because traditional radiation-hardened processors and common spacecraft processors cannot provide the necessary onboard processing capability to effectively deploy complex AI models. Advantageously, embedded AI microchips being developed for the mobile market demonstrate remarkable capability and follow similar size, weight, and power constraints that could be imposed on a space-based system. Unfortunately, many of these devices have not been qualified for use in space. Therefore, Space Test Program - Houston 9 - SpaceCube Edge-Node Intelligent Collaboration (STP-H9-SCENIC) will demonstrate inflight, cutting-edge AI applications on multiple space-based devices for next-generation onboard intelligence. SCENIC will characterize several embedded AI devices in a relevant space environment and will provide NASA and DoD with flight heritage data and lessons learned for developers seeking to enable AI/ML on future missions. Finally, SCENIC also includes new CubeSat form-factor GPS and SDR cards for guidance and navigation

    On-line Junction Temperature Estimation of SiC Power MOSFETs

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    L'abstract è presente nell'allegato / the abstract is in the attachmen

    System-on-Chip Design and Test with Embedded Debug Capabilities

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    In this project, I started with a System-on-Chip platform with embedded test structures. The baseline platform consisted of a Leon2 CPU, AMBA on-chip bus, and an Advanced Encryption Standard decryption module. The basic objective of this thesis was to use the embedded reconfigurable logic blocks for post-silicon debug and verification. The System-on-Chip platform was designed at the register transistor level and implemented in a 180-nm IBM process. Test logic instrumentation was done with DAFCA (Design Automation for Flexible Chip Architecture) Inc. pre-silicon tools. The design was then synthesized using the Synopsys Design Compiler and placed and routed using Cadence SOC Encounter. Total transistor count is about 3 million, including 1400K transistors for the debug module serving as on chip logic analyzer. Core size of the design is about 4.8mm x 4.8mm and the system is working at 151MHz. Design verification was done with Cadence NCSim. The controllability and observability of internal signals of the design is greatly increased with the help of pre-silicon tools which helps locate bugs and later fix them with the help of post-silicon tools. This helps prevent re-spins on several occasions thus saving millions of dollars. Post-silicon tools have been used to program assertions and triggers and inject numerous personalities into the reconfigurable fabric which has greatly increased the versatility of the circuit

    Multilevel Runtime Verification for Safety and Security Critical Cyber Physical Systems from a Model Based Engineering Perspective

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    Advanced embedded system technology is one of the key driving forces behind the rapid growth of Cyber-Physical System (CPS) applications. CPS consists of multiple coordinating and cooperating components, which are often software-intensive and interact with each other to achieve unprecedented tasks. Such highly integrated CPSs have complex interaction failures, attack surfaces, and attack vectors that we have to protect and secure against. This dissertation advances the state-of-the-art by developing a multilevel runtime monitoring approach for safety and security critical CPSs where there are monitors at each level of processing and integration. Given that computation and data processing vulnerabilities may exist at multiple levels in an embedded CPS, it follows that solutions present at the levels where the faults or vulnerabilities originate are beneficial in timely detection of anomalies. Further, increasing functional and architectural complexity of critical CPSs have significant safety and security operational implications. These challenges are leading to a need for new methods where there is a continuum between design time assurance and runtime or operational assurance. Towards this end, this dissertation explores Model Based Engineering methods by which design assurance can be carried forward to the runtime domain, creating a shared responsibility for reducing the overall risk associated with the system at operation. Therefore, a synergistic combination of Verification & Validation at design time and runtime monitoring at multiple levels is beneficial in assuring safety and security of critical CPS. Furthermore, we realize our multilevel runtime monitor framework on hardware using a stream-based runtime verification language

    Determination of correct operation and behaviour of a structured amorphous surface

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    A recurring theme in intelligent environments is the intelligent surface composed of nanoscale processing units (smart dust). Such a surface (iSurface) can be considered an amorphous computer composed of a large array of identical processing units (iCells) each with its own sensor/effectors. An important requirement of such a surface is the need for a fast, reliable method to determine iCell operation, performance and code integrity. Any practical solution must fulfil certain criteria. First the impact on intercellular data communication bandwidth must be kept to a minimum, this is particularly important in high density, high speed iSurface applications such as high resolution video display. Previous work on processor profiling offered a possible solution in the form of metrics derived from profiling. This thesis describes a method developed to create long (>=32 bit) stable, robust metrics using a profiling technique that represents the current operational state of an iCell and thus enabling the quick exchange of diagnostics between iCells along with data traffic. Key requirements in the development of this system were fast acquisition of diagnostic variables, minimal affect on normal operation and the possibility of a hardware implementation which could be completely non intrusive in operation. The hardware developed fulfilled all these criteria in particular a novel method to create a stable metric that could determine compromised or incorrectly loaded code was developed. The metric of code integrity had both attributes of stability and responsiveness to change, something that has proven difficult to attain before. The uniqueness of the metrics produced by the hardware was also investigated and was determined to be very good and metric bit length was efficiently used. Impact on processor performance was also deemed acceptable at 2.31% and the developed architecture could theoretically be implemented in ‘system on chip’ (SOC) with zero processor overheads

    Embedded System for Biometric Identification

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    Developing Firmware for Space Weather Probes 2 Using HDL Coder

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    GPS and wireless communications are affected by interference from the ionosphere. Space weather affects plasma in the ionosphere, causing communication disruptions and reliability issues. To better understand how space weather affects the ionosphere, instruments are flown in space to collect data about the electrical characteristics of plasma in the ionosphere. Space systems require a lot of time and effort to develop and test. This thesis explores how a high level tool can be used to simplify the process and some obstacles that still exist with developing some space systems. To do this, the firmware architecture of a new version of the Space Weather Probes (SWP) was developed and documented in this thesis

    Controller for a pressure and humidity instrument in Martian atmosphere

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    Finnish Meteorological Institute (FMI) is building a pressure and a humidity instrument for the ExoMars EDM Mars lander of European Space Agency, slated for launch in 2016. The instruments, part of a science package called DREAMS, build on the experience gained on previous meteorological Mars instrument missions participated by FMI. The instruments are based on capacitive Vaisala Barocap and Humicap sensor technologies. Traditionally, the FMI pressure and humidity instruments have been controlled by Field-Programmable Gate Array (FPGA) chips. These components are reliable, but relatively expensive, power-hungry, slow to develop and lack the ability for an in-flight update. This thesis presents a novel approach for controlling these instruments, by developing flight software for performing measurements with the DREAMS-P pressure and DREAMS-H humidity instruments. This design utilizes a commercial automotive microcontroller unit, resulting in a low-power, modi able and scalable system. The successful design and testing of the instrument controller software and functionality is presented.Ilmatieteen laitos rakentaa DREAMS-P paine- ja DREAMS-H kosteusinstrumenttia osana Euroopan avaruusjärjestö on 2016 laukaistavaa ExoMars EDM Marslaskeutujaprojektia. Ilmatieteen laitoksen aiempiin Mars-mittalaiteprojekteihin ja Vaisalan Barocap sekä Humicap anturiteknologioihin pohjautuvat instrumentit ovat osa EDM-laskeutujan DREAMS-instrumenttipakettia. Ilmatieteen laitoksen paine- ja kosteusintrumentit ovat perinteisesti pohjautuneet FPGA-piireihin (Field-Programmable Gate Array). Nämä piirit ovat luotettavia, mutta verrattain kalliita ja omaavat suurehkon tehonkulutuksen. Ohjelmistokehitys FPGA-piireillä on myös verrattain hidasta, eivätkä ne pysty itsenäisiin avaruuslennon aikaisiin päivityksiin. Tämä diplomityö esittelee uudenlaisen ohjelmistoratkaisun DREAMS-P paine- ja DREAMS-H kosteusinstrumenttien ohjaamiseen. Järjestelmä perustuu kaupalliseen, autoteollisuuden käyttöön suunniteltuun mikrokontrolleriin. Mikrokontrollerin käyttö mahdollistaa vähän tehoa kuluttavan, sekä helposti muokattavan ja laajennettavan järjestelmän rakentamisen. Työssä esitellään tämän DREAMS-P ja DREAMS-H -instrumentteja ohjaavan kontrollerin ohjelmiston suunnittelu ja testaus.

    KM3NeT front-end and readout electronics system: hardware, firmware, and software

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    [EN] The KM3NeT research infrastructure being built at the bottom of the Mediterranean Sea will host water-Cherenkov telescopes for the detection of cosmic neutrinos. The neutrino telescopes will consist of large volume three-dimensional grids of optical modules to detect the Cherenkov light from charged particles produced by neutrino-induced interactions. Each optical module houses 31 3-in. photomultiplier tubes, instrumentation for calibration of the photomultiplier signal and positioning of the optical module, and all associated electronics boards. By design, the total electrical power consumption of an optical module has been capped at seven Watts. We present an overview of the front-end and readout electronics system inside the optical module, which has been designed for a 1-ns synchronization between the clocks of all optical modules in the grid during a life time of at least 20 years.The authors acknowledge financial support from the funding agencies: Agence Nationale de la Recherche (Grant No. ANR-15-CE31-0020), Centre National de la Recherche Scientifique (CNRS), Commission Europeenne (FEDER fund and Marie Curie Program), Institut Universitaire de France (IUF), IdEx program and UnivEarthS Labex program at Sorbonne Paris Cite (Grant Nos. ANR-10-LABX-0023 and ANR-11-IDEX-0005-02), Paris Ile-de-France Region, France; Shota Rustaveli National Science Foundation of Georgia (SRNSFG, Grant No. FR-18-1268), Georgia; Deutsche Forschungsgemeinschaft (DFG), Germany; The General Secretariat of Research and Technology (GSRT), Greece; Istituto Nazionale di Fisica Nucleare (INFN), Ministero dell'Istruzione, dell'Universita e della Ricerca (MIUR), PRIN 2017 program (Grant NAT-NET 2017W4HA7S) Italy; Ministry of Higher Education, Scientific Research and Professional Training, Morocco; Nederlandse organisatie voor Wetenschappelijk Onderzoek (NWO), the Netherlands; The National Science Centre, Poland (2015/18/E/ST2/00758); National Authority for Scientific Research (ANCS), Romania; Plan Estatal de Investigacion [refs. FPA2015-65150-C3-1-P, -2-P and -3-P, (MINECO/FEDER)], Severo Ochoa Centre of Excellence program (MINECO), Red Consolider MultiDark (ref. FPA2017-90566-REDC, MINECO), and Prometeo and Grisolia programs (Generalitat Valenciana), "la Caixa" Foundation (ID 100010434) through the fellowship LCF/BQ/IN17/11620019, and the European Union's Horizon 2020 research and innovation programme under the Marie Sklodowska-Curie Grant Agreement No. 713673, Spain.Aiello, S.; Ameli, F.; Andre, M.; Androulakis, G.; Anghinolfi, M.; Anton, G.; Ardid Ramírez, M.... (2019). KM3NeT front-end and readout electronics system: hardware, firmware, and software. Journal of Astronomical Telescopes, Instruments, and Systems. 5(4):1-15. https://doi.org/10.1117/1.JATIS.5.4.046001S1155
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