Advances in optimal routing through computer networks

The optimal routing problem is defined. Progress in solving the problem during the previous decade is reviewed, with special emphasis on technical developments made during the last few years. The relationships between the routing, the throughput, and the switching technology used are discussed and their future trends are reviewed. Economic aspects are also briefly considered. Modern technical approaches for handling the routing problems and, more generally, the flow control problems are reviewed

Portable Tor Router: Easily Enabling Web Privacy for Consumers

On-line privacy is of major public concern. Unfortunately, for the average consumer, there is no simple mechanism to browse the Internet privately on multiple devices. Most available Internet privacy mechanisms are either expensive, not readily available, untrusted, or simply provide trivial information masking. We propose that the simplest, most effective and inexpensive way of gaining privacy, without sacrificing unnecessary amounts of functionality and speed, is to mask the user's IP address while also encrypting all data. We hypothesized that the Tor protocol is aptly suited to address these needs. With this in mind we implemented a Tor router using a single board computer and the open-source Tor protocol code. We found that our proposed solution was able to meet five of our six goals soon after its implementation: cost effectiveness, immediacy of privacy, simplicity of use, ease of execution, and unimpaired functionality. Our final criterion of speed was sacrificed for greater privacy but it did not fall so low as to impair day-to-day functionality. With a total cost of roughly $100.00 USD and a speed cap of around 2 Megabits per second we were able to meet our goal of an affordable, convenient, and usable solution to increased on-line privacy for the average consumer.Comment: 6 pages, 5 figures, IEEE ICCE Conferenc

Application of advanced on-board processing concepts to future satellite communications systems: Bibliography

Abstracts are presented of a literature survey of reports concerning the application of signal processing concepts. Approximately 300 references are included

System efficiency of a microwave power tube with a multistage depressed collector

The efficiencies of a microwave power tube with a multistage depressed collector and of the power supply driving the tube are computed. An analytical expression for the collector efficiency, which includes the effect of secondary emission and the radial component of velocity, is derived for a hypothetical current probability distribution function. In addition, collector efficiency is calculated with the aid of a digital computer for a specific current distribution. The efficiency of the power supply required to operate the tube in a space environment is estimated by using a simple parallel inverter system

Control Plane Hardware Design for Optical Packet Switched Data Centre Networks

Optical packet switching for intra-data centre networks is key to addressing traffic requirements. Photonic integration and wavelength division multiplexing (WDM) can overcome bandwidth limits in switching systems. A promising technology to build a nanosecond-reconfigurable photonic-integrated switch, compatible with WDM, is the semiconductor optical amplifier (SOA). SOAs are typically used as gating elements in a broadcast-and-select (B\&S) configuration, to build an optical crossbar switch. For larger-size switching, a three-stage Clos network, based on crossbar nodes, is a viable architecture. However, the design of the switch control plane, is one of the barriers to packet switching; it should run on packet timescales, which becomes increasingly challenging as line rates get higher. The scheduler, used for the allocation of switch paths, limits control clock speed. To this end, the research contribution was the design of highly parallel hardware schedulers for crossbar and Clos network switches. On a field-programmable gate array (FPGA), the minimum scheduler clock period achieved was 5.0~ns and 5.4~ns, for a 32-port crossbar and Clos switch, respectively. By using parallel path allocation modules, one per Clos node, a minimum clock period of 7.0~ns was achieved, for a 256-port switch. For scheduler application-specific integrated circuit (ASIC) synthesis, this reduces to 2.0~ns; a record result enabling scalable packet switching. Furthermore, the control plane was demonstrated experimentally. Moreover, a cycle-accurate network emulator was developed to evaluate switch performance. Results showed a switch saturation throughput at a traffic load 60\% of capacity, with sub-microsecond packet latency, for a 256-port Clos switch, outperforming state-of-the-art optical packet switches