Continuous Transmission of Spatially Coupled LDPC Code Chains

We propose a novel encoding/transmission scheme called continuous chain (CC) transmission that is able to improve the finite-length performance of a system using spatially coupled low-density parity-check (SC-LDPC) codes. In CC transmission, instead of transmitting a sequence of independent code words from a terminated SC-LDPC code chain, we connect multiple chains in a layered format, where encoding, transmission, and decoding are performed in a continuous fashion. The connections between chains are created at specific points, chosen to improve the finite-length performance of the code structure under iterative decoding. We describe the design of CC schemes for different SC-LDPC code ensembles constructed from protographs: a (J,K) -regular SC-LDPC code chain, a spatially coupled repeat-accumulate (SC-RA) code, and a spatially coupled accumulate-repeat-jagged-accumulate (SC-ARJA) code. In all cases, significant performance improvements are reported and it is shown that using CC transmission only requires a small increase in decoding complexity and decoding delay with respect to a system employing a single SC-LDPC code chain for transmission.This material is based upon work supported in part by the National Science Foundation under Grant Nos. CCF-1161754 and CCSS-1710920, in part by NSERC Canada, and in part by the Spanish Ministry of Economy and Competitiveness and the Spanish National Research Agency under grants TEC2016-78434-C3-3-R (AEI/FEDER, EU) and Juan de la Cierva Fellowship IJCI-2014-19150

Low-Density Parity-Check Coded High-order Modulation Schemes

In this thesis, we investigate how to support reliable data transmissions at high speeds in future communication systems, such as 5G/6G, WiFi, satellite, and optical communications. One of the most fundamental problems in these communication systems is how to reliably transmit information with a limited number of resources, such as power and spectral. To obtain high spectral efficiency, we use coded modulation (CM), such as bit-interleaved coded modulation (BICM) and delayed BICM (DBICM). To be specific, BICM is a pragmatic implementation of CM which has been largely adopted in both industry and academia. While BICM approaches CM capacity at high rates, the capacity gap between BICM and CM is still noticeable at lower code rates. To tackle this problem, DBICM, as a variation of BICM, introduces a delay module to create a dependency between multiple codewords, which enables us to exploit extrinsic information from the decoded delayed sub-blocks to improve the detection of the undelayed sub-blocks. Recent work shows that DBICM improves capacity over BICM. In addition, BICM and DBICM schemes protect each bit-channel differently, which is often referred to as the unequal error protection (UEP) property. Therefore, bit mapping designs are important for constructing pragmatic BICM and DBICM. To provide reliable communication, we have jointly designed bit mappings in DBICM and irregular low-density parity-check (LDPC) codes. For practical considerations, spatially coupled LDPC (SC-LDPC) codes have been considered as well. Specifically, we have investigated the joint design of the multi-chain SC-LDPC and the BICM bit mapper. In addition, the design of SC-LDPC codes with improved decoding threshold performance and reduced rate loss has been investigated in this thesis as well. The main body of this thesis consists of three parts. In the first part, considering Gray-labeled square M-ary quadrature amplitude modulation (QAM) constellations, we investigate the optimal delay scheme with the largest spectrum efficiency of DBICM for a fixed maximum number of delayed time slots and a given signal-to-noise ratio. Furthermore, we jointly optimize degree distributions and channel assignments of LDPC codes using protograph-based extrinsic information transfer charts. In addition, we proposed a constrained progressive edge growth-like algorithm to jointly construct LDPC codes and bit mappings for DBICM, taking the capacity of each bit-channel into account. Simulation results demonstrate that the designed LDPC-coded DBICM systems significantly outperform LDPC-coded BICM systems. In the second part, we proposed a windowed decoding algorithm for DBICM, which uses the extrinsic information of both the decoded delayed and undelayed sub-blocks, to improve the detection for all sub-blocks. We show that the proposed windowed decoding significantly outperforms the original decoding, demonstrating the effectiveness of the proposed decoding algorithm. In the third part, we apply multi-chain SC-LDPC to BICM. We investigate various connections for multi-chain SC-LDPC codes and bit mapping designs and analyze the performance of the multi-chain SC-LDPC codes over the equivalent binary erasure channels via density evolution. Numerical results demonstrate the superiority of the proposed design over existing connected-chain ensembles and over single-chain ensembles with the existing bit mapping design

Long-range-enhanced surface codes

The surface code is a quantum error-correcting code for one logical qubit, protected by spatially localized parity checks in two dimensions. Due to fundamental constraints from spatial locality, storing more logical qubits requires either sacrificing the robustness of the surface code against errors or increasing the number of physical qubits. We bound the minimal number of spatially non-local parity checks necessary to add logical qubits to a surface code while maintaining, or improving, robustness to errors. We asymptotically saturate this bound using a family of hypergraph product codes, interpolating between the surface code and constant-rate low-density parity-check codes. Fault-tolerant protocols for logical operations generalize naturally to these longer-range codes, based on those from ordinary surface codes. We provide near-term practical implementations of this code for hardware based on trapped ions or neutral atoms in mobile optical tweezers. Long-range-enhanced surface codes outperform conventional surface codes using hundreds of physical qubits, and represent a practical strategy to enhance the robustness of logical qubits to errors in near-term devices.Comment: 16 pages, 12 figures; v2 changes: fixed typos and added citation

Hardware-Conscious Wireless Communication System Design

The work at hand is a selection of topics in efficient wireless communication system design, with topics logically divided into two groups.One group can be described as hardware designs conscious of their possibilities and limitations. In other words, it is about hardware that chooses its configuration and properties depending on the performance that needs to be delivered and the influence of external factors, with the goal of keeping the energy consumption as low as possible. Design parameters that trade off power with complexity are identified for analog, mixed signal and digital circuits, and implications of these tradeoffs are analyzed in detail. An analog front end and an LDPC channel decoder that adapt their parameters to the environment (e.g. fluctuating power level due to fading) are proposed, and it is analyzed how much power/energy these environment-adaptive structures save compared to non-adaptive designs made for the worst-case scenario. Additionally, the impact of ADC bit resolution on the energy efficiency of a massive MIMO system is examined in detail, with the goal of finding bit resolutions that maximize the energy efficiency under various system setups.In another group of themes, one can recognize systems where the system architect was conscious of fundamental limitations stemming from hardware.Put in another way, in these designs there is no attempt of tweaking or tuning the hardware. On the contrary, system design is performed so as to work around an existing and unchangeable hardware limitation. As a workaround for the problematic centralized topology, a massive MIMO base station based on the daisy chain topology is proposed and a method for signal processing tailored to the daisy chain setup is designed. In another example, a large group of cooperating relays is split into several smaller groups, each cooperatively performing relaying independently of the others. As cooperation consumes resources (such as bandwidth), splitting the system into smaller, independent cooperative parts helps save resources and is again an example of a workaround for an inherent limitation.From the analyses performed in this thesis, promising observations about hardware consciousness can be made. Adapting the structure of a hardware block to the environment can bring massive savings in energy, and simple workarounds prove to perform almost as good as the inherently limited designs, but with the limitation being successfully bypassed. As a general observation, it can be concluded that hardware consciousness pays off