55,463 research outputs found
Formal Probabilistic Analysis of a Wireless Sensor Network for Forest Fire Detection
Wireless Sensor Networks (WSNs) have been widely explored for forest fire
detection, which is considered a fatal threat throughout the world. Energy
conservation of sensor nodes is one of the biggest challenges in this context
and random scheduling is frequently applied to overcome that. The performance
analysis of these random scheduling approaches is traditionally done by
paper-and-pencil proof methods or simulation. These traditional techniques
cannot ascertain 100% accuracy, and thus are not suitable for analyzing a
safety-critical application like forest fire detection using WSNs. In this
paper, we propose to overcome this limitation by applying formal probabilistic
analysis using theorem proving to verify scheduling performance of a real-world
WSN for forest fire detection using a k-set randomized algorithm as an energy
saving mechanism. In particular, we formally verify the expected values of
coverage intensity, the upper bound on the total number of disjoint subsets,
for a given coverage intensity, and the lower bound on the total number of
nodes.Comment: In Proceedings SCSS 2012, arXiv:1307.802
A Strategy Language for Testing Register Transfer Level Logic
The development of modern ICs requires a huge investment in RTL verification.
This is a reflection of brisk release schedules and the complexity of
contemporary chip designs. A major bottleneck to reaching verification closure
in such designs is the disproportionate effort expended in crafting directed
tests; which is necessary to reach those behaviors that other, more automated
testing methods fail to cover. This paper defines a novel language that can be
used to generate targeted stimuli for RTL logic and which mitigates the
complexities of writing directed tests. The main idea is to treat directed
testing as a meta-reasoning problem about simulation. Our language is both
formalized and prototyped as a proof-search strategy language in rewriting
logic. We illustrate its novel features and practical use with several
examples.published or submitted for publicatio
Anytime system level verification via parallel random exhaustive hardware in the loop simulation
System level verification of cyber-physical systems has the goal of verifying that the whole (i.e., software + hardware) system meets the given specifications. Model checkers for hybrid systems cannot handle system level verification of actual systems. Thus, Hardware In the Loop Simulation (HILS) is currently the main workhorse for system level verification. By using model checking driven exhaustive HILS, System Level Formal Verification (SLFV) can be effectively carried out for actual systems.
We present a parallel random exhaustive HILS based model checker for hybrid systems that, by simulating all operational scenarios exactly once in a uniform random order, is able to provide, at any time during the verification process, an upper bound to the probability that the System Under Verification exhibits an error in a yet-to-be-simulated scenario (Omission Probability).
We show effectiveness of the proposed approach by presenting experimental results on SLFV of the Inverted Pendulum on a Cart and the Fuel Control System examples in the Simulink distribution. To the best of our knowledge, no previously published model checker can exhaustively verify hybrid systems of such a size and provide at any time an upper bound to the Omission Probability
Developing a distributed electronic health-record store for India
The DIGHT project is addressing the problem of building a scalable and highly available information store for the Electronic Health Records (EHRs) of the over one billion citizens of India
- …