Conditioning electrical impedance mammography system

A multi-frequency Electrical Impedance Mammography (EIM) system has been developed to evaluate the conductivity and permittivity spectrums of breast tissues, which aims to improve early detection of breast cancer as a non-invasive, relatively low cost and label-free screening (or pre-screening) method. Multi-frequency EIM systems typically employ current excitations and measure differential potentials from the subject under test. Both the output impedance and system performance (SNR and accuracy) depend on the total output resistance, stray and output capacitances, capacitance at the electrode level, crosstalk at the chip and PCB levels. This makes the system design highly complex due to the impact of the unwanted capacitive effects, which substantially reduce the output impedance of stable current sources and bandwidth of the data that can be acquired. To overcome these difficulties, we present new methods to design a high performance, wide bandwidth EIM system using novel second generation current conveyor operational amplifiers based on a gyrator (OCCII-GIC) combination with different current excitation systems to cancel unwanted capacitive effects from the whole system. We reconstructed tomography images using a planar E-phantom consisting of an RSC circuit model, which represents the resistance of extra-cellular (R), intra-cellular (S) and membrane capacitance (C) of the breast tissues to validate the performance of the system. The experimental results demonstrated that an EIM system with the new design achieved a high output impedance of 10MΩ at 1MHz to at least 3MΩ at 3MHz frequency, with an average SNR and modelling accuracy of over 80dB and 99%, respectively

Design of an Active Harmonic Rejection N-Path Filter for Highly Tunable RF Channel Selection

As the number of wireless devices in the world increases, so does the demand for flexible radio receiver architectures capable of operating over a wide range of frequencies and communication protocols. The resonance-based channel-select filters used in traditional radio architectures have a fixed frequency response, making them poorly suited for such a receiver. The N-path filter is based on 1960s technology that has received renewed interest in recent years for its application as a linear high Q filter at radio frequencies. N-path filters use passive mixers to apply a frequency transformation to a baseband low-pass filter in order to achieve a high-Q band-pass response at high frequencies. The clock frequency determines the center frequency of the band-pass filter, which makes the filter highly tunable over a broad frequency range. Issues with harmonic transfer and poor attenuation limit the feasibility of using N-path filters in practice. The goal of this thesis is to design an integrated active N-path filter that improves upon the passive N-path filter’s poor harmonic rejection and limited outof- band attenuation. The integrated circuit (IC) is implemented using the CMRF8SF 130nm CMOS process. The design uses a multi-phase clock generation circuit to implement a harmonic rejection mixer in order to suppress the 3rd and 5th harmonic. The completed active N-path filter has a tuning range of 200MHz to 1GHz and the out-ofband attenuation exceeds 60dB throughout this range. The frequency response exhibits a 14.7dB gain at the center frequency and a -3dB bandwidth of 6.8MHz

Design and Implementation of a Signal Conditioning Operational Amplifier for a Reflective Object Sensor

Industrial systems often require the acquisition of real-world analog signals for several applications. Various physical phenomena such as displacement, pressure, temperature, light intensity, etc. are measured by sensors, which is a type of transducer, and then converted into a corresponding electrical signal. The electrical signal obtained from the sensor, usually a few tens mV in magnitude, is subsequently conditioned by means of amplification, filtering, range matching, isolation etc., so that the signal can be rendered for further processing and data extraction. This thesis presents the design and implementation of a general purpose op amp used to condition a reflective object sensor’s output. The op amp is used in a non-inverting configuration, as a current-to-voltage converter to transform a phototransistor current into a usable voltage. The op amp has been implemented using CMOS architecture and fabricated in AMI 0.5-µm CMOS process available through MOSIS. The thesis begins with an overview of the various circuits involving op amps used in signal conditioning circuits. Owing to the vast number of applications for sensor signal conditioning circuits, a brief discussion of an industrial sensor circuit is also illustrated. This is followed by the complete design of the op amp and its implementation in the data acquisition circuit. The op amp is then characterized using simulation results. Finally, the test setup and the measurement results are presented. The thesis concludes with an overview of some possible future work on the sensor-op amp data acquisition circuit

Design and Analysis of a General Purpose Operational Amplifier for Extreme Temperature Operation

Operational amplifiers (op amps) are key functional blocks that are used in a variety of analog subsystems such as switched-capacitor filters, analog-to-digital converters, digital-to-analog converters, voltage references and regulators, etc. There has been a growing interest in using such circuits for extreme environment electronics, in particular for electronics capable of operating down to deep-cryogenic temperatures for lunar and Martian surface explorations. This thesis presents the design and analysis of a general purpose op amp suited for “extreme environment” applications, with a wide operating temperature range of 93 K to 398 K. The op amp has been implemented using a CMOS architecture to exploit the low temperature operational advantages offered by MOS devices, such as increase in carrier mobility, increased transconductance, and improved switching speeds. The op amp has a two-stage architecture to provide high gain and also incorporates common-mode feedback around the input stage. Tracking compensation has been implemented to provide stable frequency compensation over wide temperature. The op amp has been fabricated in a commercial 0.35-μm 3.3-V SiGe BiCMOS process. The op amp has been tested for the temperature range of 93 K to 398 K and is unity-gain stable and fully functional over this range. This thesis begins with a study of the impact of temperature on MOS devices and operational amplifiers. Next, the design of the wide temperature general-purpose operational amplifier is presented along with an analysis of the common-mode feedback circuit. The op amp is then characterized using simulation results. Finally, the test setup is presented and the measurement results are compared with those from simulation

Design of a High Performance Silicon Carbide CMOS Operational Amplifier

This thesis presents the design, simulation, layout and test results of a silicon carbide (SiC) CMOS two-stage operational amplifier (op amp) with NMOS input stage. The circuit has been designed to provide a stable open-loop voltage gain (60 dB), unity-gain bandwidth (around 5 MHz) and maintain a high CMRR and PSRR within a useful input common mode range over process corners and a wide temperature range (25 °C - 300 °C). Between the two stages a Miller compensation topology is placed to improve the phase margin (around 45°). Due to the comparatively high threshold voltage values of transistors in SiC, the power supply is maintained at 15 V. There is a maximum of 21% variation in DC gain from 25 °C to 275 °C and the unity-gain bandwidth and slew rate improves with higher temperature. The major application area of this op amp is in high temperature environments where silicon (Si) integrated circuits (IC) fail to perform. In addition, the design of a second version of the operational amplifier is covered, which aims to provide more functionality and improved performance

Exploiting the bulk-driven approach in CMOS analogue amplifier design

This thesis presents a collection of new novel techniques using the bulk-driven approach, which can lead to performance enhancement in the field of CMOS analogue amplifier design under the very low-supply voltage constraints. In this thesis, three application areas of the bulk-driven approach are focused – at the input-stage of differential pairs, at the source followers, and at the cascode devices. For the input stage of differential pairs, this thesis proposes two new novel circuit design techniques. One of them utilises the concept of the replica-biased scheme in order to solve the non-linearity and latch-up issues, which are the potential problems that come along with the bulk-driven approach. The other proposed circuit design technique utilises the flipped voltage scheme and the Quasi-Floating Gate technique in order to achieve low-power high-speed performances, and furthermore the reversed-biased diode concept to overcome the issue of degraded input impedance characteristics that come along with the bulk-driven approach. Applying the bulk-driven approach in source followers is a new type of circuit blocks in CMOS analogue field, in which to the author’s best knowledge has not been proposed at any literatures in the past. This thesis presents the bulk-driven version of the flipped voltage followers and super source followers, which can lead to eliminating the DC level shift. Furthermore, a technique for programming the DC level shift less than the threshold voltage of a MOSFET, which cannot be achieved by conventional types of source followers, is presented. The effectiveness of the cascode device using the bulk-driven approach is validated by implementing it in a complete schematics design of a fully differential bulk-driven operational transcoductance amplifier (OTA). This proposal leads to solving the lowtranconductance problem of a bulk-driven differential pair, and in effect the open loop gain of the OTA exceeds 60dB using a 0.35μm CMOS technology. The final part of this thesis provides the study result of the input capacitance of a bulk-driven buffer. To verify the use of the BSIM3 MOSFET model in the simulation for predicting the input capacitance, the measurement data of the fabricated device are compared with the postlayout simulation results

Low-Voltage Analog Circuit Design Using the Adaptively Biased Body-Driven Circuit Technique

The scaling of MOSFET dimensions and power supply voltage, in conjunction with an increase in system- and circuit-level performance requirements, are the most important factors driving the development of new technologies and design techniques for analog and mixed-signal integrated circuits. Though scaling has been a fact of life for analog circuit designers for many years, the approaching 1-V and sub-1-V power supplies, combined with applications that have increasingly divergent technology requirements, means that the analog and mixed-signal IC designs of the future will probably look quite different from those of the past. Foremost among the challenges that analog designers will face in highly scaled technologies are low power supply voltages, which limit dynamic range and even circuit functionality, and ultra-thin gate oxides, which give rise to significant levels of gate leakage current. The goal of this research is to develop novel analog design techniques which are commensurate with the challenges that designers will face in highly scaled CMOS technologies. To that end, a new and unique body-driven design technique called adaptive gate biasing has been developed. Adaptive gate biasing is a method for guaranteeing that MOSFETs in a body-driven simple current mirror, cascode current mirror, or regulated cascode current source are biased in saturation—independent of operating region, temperature, or supply voltage—and is an enabling technology for high-performance, low-voltage analog circuits. To prove the usefulness of the new design technique, a body-driven operational amplifier that heavily leverages adaptive gate biasing has been developed. Fabricated on a 3.3-V/0.35-μm partially depleted silicon-onv-insulator (PD-SOI) CMOS process, which has nMOS and pMOS threshold voltages of 0.65 V and 0.85 V, respectively, the body-driven amplifier displayed an open-loop gain of 88 dB, bandwidth of 9 MHz, and PSRR greater than 50 dB at 1-V power supply